![4.6MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)](/images/new-backgrounds/123159/123159149x1.webp)
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MDIO Registers
4.6MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 32 and described in Table 30.
Figure 32. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
31 |
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| 16 |
| Reserved |
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15 | 2 | 1 | 0 |
Reserved |
| LINKINTMASKED | |
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LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect;
Table 30. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
LINKINTMASKED | MDIO Link change interrupt, masked value. When asserted, a bit indicates that there was an MDIO | ||
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| link change event (that is, change in the LINK register) corresponding to the PHY address in the |
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| USERPHYSEL register and the corresponding LINKINTENB bit was set. LINKINTMASKED[0] and |
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| LINKINTMASKED[1] correspond to USERPHYSEL0 and USERPHYSEL1, respectively. Writing a 1 |
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| will clear the event and writing a 0 has no effect. |
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| 0 | No MDIO link change event. |
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| 1 | An MDIO link change event (change in the LINK register) corresponding to the PHY address in |
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| MDIO user PHY select register n (USERPHYSELn) and the LINKINTENB bit in USERPHYSELn is |
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| set to 1. |
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | 75 | |
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