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Architecture

A round-robin arbitration scheme is used to schedule transactions that may be queued using both USERACCESS0 and USERACCESS1. The application software must check the status of the GO bit in USERACCESSn before initiating a new transaction, to ensure that the previous transaction has completed. The application software can use the ACK bit in USERACCESSn to determine the status of a read transaction.

2.7.2.1Initializing the MDIO Module

The following steps are performed by the application software or device driver to initialize the MDIO device:

1.Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL).

2.Enable the MDIO module by setting the ENABLE bit in CONTROL.

3.The MDIO PHY alive status register (ALIVE) can be read in polling fashion until a PHY connected to the system responded, and the MDIO PHY link status register (LINK) can determine whether this PHY already has a link.

4.Setup the appropriate PHY addresses in the MDIO user PHY select register (USERPHYSELn), and set the LINKINTENB bit to enable a link change event interrupt if desirable.

5.If an interrupt on general MDIO register access is desired, set the corresponding bit in the MDIO user command complete interrupt mask set register (USERINTMASKSET) to use the MDIO user access register (USERACCESSn). Since only one PHY is used in this device, the application software can use one USERACCESSn to trigger a completion interrupt; the other USERACCESSn is not setup.

2.7.2.2Writing Data To a PHY Register

The MDIO module includes a user access register (USERACCESSn) to directly access a specified PHY device. To write a PHY register, perform the following:

1.Check to ensure that the GO bit in the MDIO user access register (USERACCESSn) is cleared.

2.Write to the GO, WRITE, REGADR, PHYADR, and DATA bits in USERACCESSn corresponding to the PHY and PHY register you want to write.

3.The write operation to the PHY is scheduled and completed by the MDIO module. Completion of the write operation can be determined by polling the GO bit in USERACCESSn for a 0.

4.Completion of the operation sets the corresponding USERINTRAW bit (0 or 1) in the MDIO user command complete interrupt register (USERINTRAW) corresponding to USERACCESSn used. If interrupts have been enabled on this bit using the MDIO user command complete interrupt mask set register (USERINTMASKSET), then the bit is also set in the MDIO user command complete interrupt register (USERINTMASKED) and an interrupt is triggered on the CPU.

2.7.2.3Reading Data From a PHY Register

The MDIO module includes a user access register (USERACCESSn) to directly access a specified PHY device. To read a PHY register, perform the following:

1.Check to ensure that the GO bit in the MDIO user access register (USERACCESSn) is cleared.

2.Write to the GO, REGADR, and PHYADR bits in USERACCESSn corresponding to the PHY and PHY register you want to read.

3.The read data value is available in the DATA bits in USERACCESSn after the module completes the read operation on the serial bus. Completion of the read operation can be determined by polling the GO and ACK bits in USERACCESSn. Once the GO bit has cleared, the ACK bit is set on a successful read.

4.Completion of the operation sets the corresponding USERINTRAW bit (0 or 1) in the MDIO user command complete interrupt register (USERINTRAW) corresponding to USERACCESSn used. If interrupts have been enabled on this bit using the MDIO user command complete interrupt mask set register (USERINTMASKSET), then the bit is also set in the MDIO user command complete interrupt register (USERINTMASKED) and an interrupt is triggered on the CPU.

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Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x manual Initializing the Mdio Module, Writing Data To a PHY Register
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TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

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