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Texas Instruments TMS320DM646x EMAC Control Module Interrupt Control Register CMINTCTRL, Field

Models: TMS320DM646x

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3.4EMAC Control Module Interrupt Control Register (CMINTCTRL)

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EMAC Control Module Registers

3.4EMAC Control Module Interrupt Control Register (CMINTCTRL)

The interrupt control register (CMINTCTRL) is shown in Figure 16 and described in Table 13.

Figure 16. EMAC Control Module Interrupt Control Register (CMINTCTRL)

31	30		18	17	16
Reserved		Reserved		INTPACEEN
R/W-0		R-0			R/W-0
15	12	11			0
	Reserved		INTPRESCALE
	R-0		R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

		Table 13. EMAC Control Module Interrupt Control Register (CMINTCTRL)
			Field Descriptions
Bit	Field	Value	Description
31	Reserved	0	Reserved
30-18	Reserved	0	Reserved
17-16	INTPACEEN	0-3h	Interrupt pacing enable.
			Bit 16 = 1; enables Rx_Pulse Pacing; = 0, disables pacing
			Bit 17 = 1; enables Tx_Pulse Pacing; = 0, disables pacing
15-12	Reserved	0	Reserved
11-0	INTPRESCALE	0-7FFh	Interrupt counter prescaler. The number of peripheral clock periods in 4 μs.

SPRUEQ6–December 2007	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	63
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Texas Instruments TMS320DM646x manual EMAC Control Module Interrupt Control Register CMINTCTRL, Field Descriptions, Value

Contents

TMS320DM646x DMSoC Ethernet Media Access Controller EMAC Users GuideManagement Data Input/Output MDIO Module Submit Documentation Feedback SPRUEQ6-DecemberContents PHY Acknowledge Status Register ALIVE MAC Hash Address Register 1 MACHASH1 List of Figures List of FiguresReceive Interrupt Mask Set Register RXINTMASKSET List of Tables FIFO Control Register FIFOCONTROL Field Descriptions Soft Reset Register SOFTRESET Field DescriptionsMAC Control Register MACCONTROL Field Descriptions MAC Status Register MACSTATUS Field DescriptionsNotational Conventions Read This FirstPreface About This ManualRead This First Related Documentation From Texas Instruments1.1 Purpose of the Peripheral Users Guide1.2 Features 1 IntroductionFigure 1. EMAC and MDIO Block Diagram 1.3 Functional Block Diagram2.1.1 MII Clocking 1.4 Industry Standards Compliance Statement2 Architecture 2.1 Clock Control2.3.1 Media Independent Interface MII Connections 2.3 Signal DescriptionsFigure 2. Ethernet Configuration-MII Connections 2.2 Memory MapType Table 1. EMAC and MDIO Signals for MII InterfaceSignal ArchitectureMTCLK GMTCLK RFTCLK MTXD7−0 MTXEN MCOL MCRS MRCLK MRXD7−0 MRXDV MRXER Figure 3. Ethernet Configuration-GMII ConnectionsTable 2. EMAC and MDIO Signals for GMII Interface 2.3.2 Gigabit Media Independent Interface GMII ConnectionsType Table 2. EMAC and MDIO Signals for GMII Interface continuedSignal ArchitectureTable 3. Ethernet Frame Description 2.4 Ethernet Protocol Overview2.4.1 Ethernet Frame Format Figure 4. Ethernet Frame FormatFigure 5. Basic Descriptor Format 2.4.2 Ethernet’s Multiple Access Protocol2.5 Programming Interface 2.5.1 Packet Buffer DescriptorsFigure 6. Typical Descriptor Linked List Table 4. Basic Descriptor Description2.5.2 Transmit and Receive Descriptor Queues 2.5.3 Transmit and Receive EMAC Interrupts Architecture 2.5.4 Transmit Buffer Descriptor FormatFigure 7. Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure Format2.5.4.4 Buffer Length 2.5.4.1 Next Descriptor Pointer2.5.4.2 Buffer Pointer 2.5.4.3 Buffer Offset2.5.4.10 Teardown Complete TDOWNCMPLT Flag 2.5.4.7 End of Packet EOP Flag2.5.4.8 Ownership OWNER Flag 2.5.4.9 End of Queue EOQ FlagFigure 8. Receive Buffer Descriptor Format 2.5.5 Receive Buffer Descriptor Format2.5.5.1 Next Descriptor Pointer 2.5.5.2 Buffer Pointer2.5.5.3 Buffer Offset Example 2. Receive Buffer Descriptor in C Structure Format2.5.5.7 End of Packet EOP Flag 2.5.5.4 Buffer Length2.5.5.5 Packet Length 2.5.5.6 Start of Packet SOP Flag2.5.5.10 Teardown Complete TDOWNCMPLT Flag 2.5.5.18 Code Error CODEERROR Flag2.5.5.19 Alignment Error ALIGNERROR Flag 2.5.5.20 CRC Error CRCERROR Flag2.6.1 Internal Memory Figure 9. EMAC Control Module Block Diagram2.6 EMAC Control Module 2.5.5.21 No Match NOMATCH Flag2.6.3.2 Receive Pulse Interrupt 2.6.3 Interrupt ControlTable 5. EMAC Control Module Interrupts 2.6.3.1 Transmit Pulse Interrupt2.6.3.3 Receive Threshold Pulse Interrupt 2.6.3.4 Miscellaneous Pulse Interrupt2.6.4 Interrupt Pacing 2.7.1.1 MDIO Clock Generator Figure 10. MDIO Module Block Diagram2.7 MDIO Module 2.7.1 MDIO Module Components2.7.2 MDIO Module Operational Overview 2.7.1.4 PHY Register User Access2.7.1.2 Global PHY Detection and Link State Monitoring 2.7.1.3 Active PHY Monitoring2.7.2.1 Initializing the MDIO Module 2.7.2.2 Writing Data To a PHY Register2.7.2.3 Reading Data From a PHY Register Example 3. MDIO Register Access Macros 2.7.2.4 Example of MDIO Register Access Code2.8.1.1 Receive DMA Engine Figure 11. EMAC Module Block Diagram2.8 EMAC Module 2.8.1 EMAC Module Components2.8.1.5 Transmit DMA Engine 2.8.1.12 Clock and Reset Logic2.8.1.3 MAC Receiver 2.8.1.4 Receive Address2.8.2 EMAC Module Operational Overview 2.9.1.2 Receive Inter-Frame Interval 2.9 Media Independent Interface MII2.9.1 Data Reception 2.9.1.1 Receive Control2.9.1.3.2 IEEE 802.3x-Based Receive Buffer Flow Control 2.9.1.3.1 Collision-Based Receive Buffer Flow Control2.9.2.3 Adaptive Performance Optimization APO 2.9.2 Data Transmission2.9.2.1 Transmit Control 2.9.2.2 CRC Insertion2.9.2.7 Speed, Duplex, and Pause Frame Support 2.9.2.6 Transmit Flow Control2.10.1 Receive DMA Host Configuration 2.10 Packet Receive Operation2.10.2 Receive Channel Enabling 2.10.3 Receive Address Matching 2.10.4 Hardware Receive QOS Support2.10.5 Host Free Buffer Tracking 2.10.7 Receive Frame Classification 2.10.6 Receive Channel TeardownRXCEFEN 2.10.8 Promiscuous Receive ModeTable 6. Receive Frame Treatment Summary RXCAFENTable 6. Receive Frame Treatment Summary continued 2.10.9 Receive OverrunTable 7. Middle of Frame Overrun Treatment 2.11.2 Transmit Channel Teardown 2.11.1 Transmit DMA Host Configuration2.11 Packet Transmit Operation 2.12 Receive and Transmit Latency2.14 Reset Considerations 2.14.1 Software Reset Considerations2.13 Transfer Node Priority 2.15.2 EMAC Control Module Initialization 2.14.2 Hardware Reset Considerations2.15 Initialization 2.15.1 Enabling the EMAC/MDIO PeripheralExample 4. EMAC Control Module Initialization Code ArchitectureSubmit Documentation Feedback Example 5. MDIO Module Initialization Code 2.15.3 MDIO Module Initialization2.15.4 EMAC Module Initialization 2.16.1.1 Receive Threshold Interrupts Figure 12. EMAC Control Module Interrupt Logic Diagram2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests2.16.1.3 Receive Packet Completion Interrupts 2.16.1.2 Transmit Packet Completion Interrupts2.16.1.4 Statistics Interrupt 2.16.1.5 Host Error Interrupt2.16.3 Proper Interrupt Processing 2.16.2.2 User Access Completion Interrupt2.16.2 MDIO Module Interrupt Events and Requests 2.16.2.1 Link Change Interrupt2.17 Power Management 2.18 Emulation ConsiderationsTable 8. Emulation Control Field Descriptions 3 EMAC Control Module Registers3.1 EMAC Control Module Identification and Version Register CMIDVER Table 9. EMAC Control Module RegistersFigure 15. EMAC Control Module Emulation Control Register CMEMCONTROL 3.2 EMAC Control Module Software Reset Register CMSOFTRESETFigure 14. EMAC Control Module Software Reset Register CMSOFTRESET 3.3 EMAC Control Module Emulation Control Register CMEMCONTROLField Descriptions 3.4 EMAC Control Module Interrupt Control Register CMINTCTRLFigure 16. EMAC Control Module Interrupt Control Register CMINTCTRL Table 13. EMAC Control Module Interrupt Control Register CMINTCTRLCMRXTHRESHINTEN 3.5 EMAC Control Module Receive Threshold Interrupt Enable Register3.6 EMAC Control Module Receive Interrupt Enable Register CMRXINTEN CMRXTHRESHINTENField Descriptions 3.7 EMAC Control Module Transmit Interrupt Enable Register CMTXINTENField Descriptions CMRXTHRESHINTSTAT Field Descriptions 3.9 EMAC Control Module Receive Threshold Interrupt Status RegisterCMRXTHRESHINTSTAT CMRXTHRESHINTSTATField Descriptions Field Descriptions 3.13 EMAC Control Module Receive Interrupts per Millisecond Register CMRXINTMAX Figure 27. MDIO Version Register VERSION 4 MDIO Registers4.1 MDIO Version Register VERSION Table 24. Management Data Input/Output MDIO RegistersMDIO Registers 4.2 MDIO Control Register CONTROLFigure 28. MDIO Control Register CONTROL Table 26. MDIO Control Register CONTROL Field DescriptionsTable 27. PHY Acknowledge Status Register ALIVE Field Descriptions 4.3 PHY Acknowledge Status Register ALIVE4.4 PHY Link Status Register LINK Figure 29. PHY Acknowledge Status Register ALIVEField Descriptions 4.5 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAWField Descriptions 4.6 MDIO Link Status Change Interrupt Masked Register LINKINTMASKEDField Descriptions 4.7 MDIO User Command Complete Interrupt Unmasked Register USERINTRAWField Descriptions Field Descriptions Field Descriptions Figure 36. MDIO User Command Complete Interrupt Mask Clear RegisterFigure 36 and described in Table USERINTMASKCLEARMDIO Registers 4.11 MDIO User Access Register 0 USERACCESS0Figure 37. MDIO User Access Register 0 USERACCESS0 Table 35. MDIO User Access Register 0 USERACCESS0 Field DescriptionsField 4.12 MDIO User PHY Select Register 0 USERPHYSEL0Figure 38. MDIO User PHY Select Register 0 USERPHYSEL0 MDIO RegistersMDIO Registers 4.13 MDIO User Access Register 1 USERACCESS1Figure 39. MDIO User Access Register 1 USERACCESS1 Table 37. MDIO User Access Register 1 USERACCESS1 Field DescriptionsField 4.14 MDIO User PHY Select Register 1 USERPHYSEL1Figure 40. MDIO User PHY Select Register 1 USERPHYSEL1 MDIO RegistersAcronym 5 Ethernet Media Access Controller EMAC RegistersTable 39. Ethernet Media Access Controller EMAC Registers Ethernet Media Access Controller EMAC RegistersAcronym Table 39. Ethernet Media Access Controller EMAC Registers continuedEthernet Media Access Controller EMAC Registers OffsetAcronym Table 39. Ethernet Media Access Controller EMAC Registers continuedEthernet Media Access Controller EMAC Registers OffsetFigure 42. Transmit Control Register TXCONTROL 5.1 Transmit Identification and Version Register TXIDVER5.2 Transmit Control Register TXCONTROL Figure 41. Transmit Identification and Version Register TXIDVERTable 42. Transmit Teardown Register TXTEARDOWN Field Descriptions Ethernet Media Access Controller EMAC Registers5.3 Transmit Teardown Register TXTEARDOWN Figure 43. Transmit Teardown Register TXTEARDOWNFigure 45. Receive Control Register RXCONTROL 5.4 Receive Identification and Version Register RXIDVER5.5 Receive Control Register RXCONTROL Figure 44. Receive Identification and Version Register RXIDVERTable 45. Receive Teardown Register RXTEARDOWN Field Descriptions Ethernet Media Access Controller EMAC Registers5.6 Receive Teardown Register RXTEARDOWN Figure 46. Receive Teardown Register RXTEARDOWNField Ethernet Media Access Controller EMAC Registers5.7 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Figure 47. Transmit Interrupt Status Unmasked Register TXINTSTATRAWField Ethernet Media Access Controller EMAC Registers5.8 Transmit Interrupt Status Masked Register TXINTSTATMASKED Figure 48. Transmit Interrupt Status Masked Register TXINTSTATMASKEDField Ethernet Media Access Controller EMAC Registers5.9 Transmit Interrupt Mask Set Register TXINTMASKSET Figure 49. Transmit Interrupt Mask Set Register TXINTMASKSETField Ethernet Media Access Controller EMAC Registers5.10 Transmit Interrupt Mask Clear Register TXINTMASKCLEAR Figure 50. Transmit Interrupt Mask Clear Register TXINTMASKCLEARTable 50. MAC Input Vector Register MACINVECTOR Field Descriptions 5.11 MAC Input Vector Register MACINVECTOR5.12 MAC End Of Interrupt Vector Register MACEOIVECTOR Figure 51. MAC Input Vector Register MACINVECTORField Ethernet Media Access Controller EMAC Registers5.13 Receive Interrupt Status Unmasked Register RXINTSTATRAW Figure 53. Receive Interrupt Status Unmasked Register RXINTSTATRAWField Ethernet Media Access Controller EMAC Registers5.14 Receive Interrupt Status Masked Register RXINTSTATMASKED Figure 54. Receive Interrupt Status Masked Register RXINTSTATMASKEDField Ethernet Media Access Controller EMAC Registers5.15 Receive Interrupt Mask Set Register RXINTMASKSET Figure 55. Receive Interrupt Mask Set Register RXINTMASKSETField Ethernet Media Access Controller EMAC Registers5.16 Receive Interrupt Mask Clear Register RXINTMASKCLEAR Figure 56. Receive Interrupt Mask Clear Register RXINTMASKCLEARFigure 58. MAC Interrupt Status Masked Register MACINTSTATMASKED 5.17 MAC Interrupt Status Unmasked Register MACINTSTATRAW5.18 MAC Interrupt Status Masked Register MACINTSTATMASKED Figure 57. MAC Interrupt Status Unmasked Register MACINTSTATRAWFigure 60. MAC Interrupt Mask Clear Register MACINTMASKCLEAR 5.19 MAC Interrupt Mask Set Register MACINTMASKSET5.20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR Figure 59. MAC Interrupt Mask Set Register MACINTMASKSETField Descriptions Value Ethernet Media Access Controller EMAC RegistersField Descriptions continued FieldValue Ethernet Media Access Controller EMAC RegistersField Descriptions continued FieldField 5.22 Receive Unicast Enable Set Register RXUNICASTSETFigure 62. Receive Unicast Enable Set Register RXUNICASTSET Ethernet Media Access Controller EMAC RegistersField Ethernet Media Access Controller EMAC Registers5.23 Receive Unicast Clear Register RXUNICASTCLEAR Figure 63. Receive Unicast Clear Register RXUNICASTCLEARTable 63. Receive Maximum Length Register RXMAXLEN Field Descriptions 5.24 Receive Maximum Length Register RXMAXLEN5.25 Receive Buffer Offset Register RXBUFFEROFFSET Figure 64. Receive Maximum Length Register RXMAXLENField Descriptions Field Descriptionsdescribed in Table 5.28 Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFERTable 68. MAC Control Register MACCONTROL Field Descriptions Ethernet Media Access Controller EMAC Registers5.29 MAC Control Register MACCONTROL Figure 69. MAC Control Register MACCONTROLValue FieldDescription Submit Documentation FeedbackTable 69. MAC Status Register MACSTATUS Field Descriptions Ethernet Media Access Controller EMAC Registers5.30 MAC Status Register MACSTATUS Figure 70. MAC Status Register MACSTATUSDescription Table 69. MAC Status Register MACSTATUS Field Descriptions continuedField ValueTable 70. Emulation Control Register EMCONTROL Field Descriptions 5.31 Emulation Control Register EMCONTROL5.32 FIFO Control Register FIFOCONTROL Figure 71. Emulation Control Register EMCONTROLTable 72. MAC Configuration Register MACCONFIG Field Descriptions 5.33 MAC Configuration Register MACCONFIG5.34 Soft Reset Register SOFTRESET Figure 73. MAC Configuration Register MACCONFIGFigure 76. MAC Source Address High Bytes Register MACSRCADDRHI 5.35 MAC Source Address Low Bytes Register MACSRCADDRLO5.36 MAC Source Address High Bytes Register MACSRCADDRHI Figure 75. MAC Source Address Low Bytes Register MACSRCADDRLOTable 76. MAC Hash Address Register 1 MACHASH1 Field Descriptions 5.37 MAC Hash Address Register 1 MACHASH15.38 MAC Hash Address Register 2 MACHASH2 Figure 77. MAC Hash Address Register 1 MACHASH1Table 78. Back Off Test Register BOFFTEST Field Descriptions 5.39 Back Off Test Register BOFFTEST5.40 Transmit Pacing Algorithm Test Register TPACETEST Figure 79. Back Off Random Number Generator Test Register BOFFTESTTable 80. Receive Pause Timer Register RXPAUSE Field Descriptions 5.41 Receive Pause Timer Register RXPAUSE5.42 Transmit Pause Timer Register TXPAUSE Figure 81. Receive Pause Timer Register RXPAUSETable 82. MAC Address Low Bytes Register MACADDRLO Field Descriptions Ethernet Media Access Controller EMAC Registers5.43 MAC Address Low Bytes Register MACADDRLO Figure 83. MAC Address Low Bytes Register MACADDRLOFigure 85. MAC Index Register MACINDEX 5.44 MAC Address High Bytes Register MACADDRHI5.45 MAC Index Register MACINDEX Figure 84. MAC Address High Bytes Register MACADDRHIField Descriptions 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register TXnHDP5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register RXnHDP Field DescriptionsFigure 89. Receive Channel n Completion Pointer Register RX nCP 5.48 Transmit Channel 0-7 Completion Pointer Register TXnCP5.49 Receive Channel 0-7 Completion Pointer Register RXnCP Figure 88. Transmit Channel n Completion Pointer Register TX nCP5.50.2 Broadcast Receive Frames Register RXBCASTFRAMES 5.50 Network Statistics RegistersFigure 90. Statistics Register 5.50.1 Good Receive Frames Register RXGOODFRAMES5.50.7 Receive Oversized Frames Register RXOVERSIZED 5.50.5 Receive CRC Errors Register RXCRCERRORS5.50.6 Receive Alignment/Code Errors Register RXALIGNCODEERRORS 5.50.4 Pause Receive Frames Register RXPAUSEFRAMES5.50.11 Filtered Receive Frames Register RXFILTERED 5.50.8 Receive Jabber Frames Register RXJABBER5.50.9 Receive Undersized Frames Register RXUNDERSIZED 5.50.10 Receive Frame Fragments Register RXFRAGMENTS5.50.15 Broadcast Transmit Frames Register TXBCASTFRAMES 5.50.12 Receive QOS Filtered Frames Register RXQOSFILTERED5.50.13 Receive Octet Frames Register RXOCTETS 5.50.14 Good Transmit Frames Register TXGOODFRAMES5.50.19 Transmit Collision Frames Register TXCOLLISION 5.50.16 Multicast Transmit Frames Register TXMCASTFRAMES5.50.17 Pause Transmit Frames Register TXPAUSEFRAMES 5.50.18 Deferred Transmit Frames Register TXDEFERRED5.50.22 Transmit Excessive Collision Frames Register TXEXCESSIVECOLL 5.50.24 Transmit Underrun Error Register TXUNDERRUN5.50.25 Transmit Carrier Sense Errors Register TXCARRIERSENSE 5.50.21 Transmit Multiple Collision Frames Register TXMULTICOLL5.50.27 Transmit and Receive 64 Octet Frames Register FRAME64 5.50.26 Transmit Octet Frames Register TXOCTETS5.50.33 Network Octet Frames Register NETOCTETS 5.50.36 Receive DMA Overruns Register RXDMAOVERRUNS Ethernet Media Access Controller EMAC RegistersAppendix A Appendix A GlossaryTable A-1. Physical Layer Definitions Applications power.ti.comIMPORTANT NOTICE Products