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EMAC Control Module Registers
3.5EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN)
The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in Figure 17 and described in Table 14.
Figure 17. EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN)
31 |
|
| 16 |
| Reserved |
| |
|
|
| |
15 | 8 | 7 | 0 |
Reserved |
|
| RXTHRESHEN |
|
|
LEGEND: R/W = Read/Write; R = Read only;
Table 14. EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
RXTHRESHEN[n] |
| Receive threshold interrupt (RXTHRESHPENDn) enable. Each bit controls the corresponding |
channel n receive threshold interrupt.
Bit n = 0, channel n receive threshold interrupt (RXTHRESHPENDn) is disabled.
Bit n = 1, channel n receive threshold interrupt (RXTHRESHPENDn) is enabled.
3.6EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
The receive interrupt enable register (CMRXINTEN) is shown in Figure 18 and described in Table 15.
Figure 18. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
31 |
|
| 16 |
| Reserved |
| |
|
|
| |
15 | 8 | 7 | 0 |
Reserved |
|
| RXPULSEEN |
|
|
LEGEND: R/W = Read/Write; R = Read only;
Table 15. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
RXPULSEEN[n] |
| Receive interrupt (RXPENDn) enable. Each bit controls the corresponding channel n receive | |
|
|
| interrupt. |
Bit n = 0, channel n receive interrupt (RXPENDn) is disabled.
Bit n = 1, channel n receive interrupt (RXPENDn) is enabled.
64 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | |
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