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Architecture

If the rate of transmit pulse interrupt inputs is much less than the target transmit pulse interrupt rate specified in CMTXINTMAX, then the interrupts are not blocked to the CPU. If the transmit pulse interrupt rate is greater than the specified target rate in CMTXINTMAX, the interrupt is paced at the rate specified in this register, which should be written with a value between 2 and 63 inclusive, indicating the target number of interrupts per 1 ms going to the CPU. Similarly, the number of receive interrupt pulses to the CPU is also separately controlled.

2.7MDIO Module

The MDIO module is used to manage up to 32 physical layer (PHY) devices connected to the Ethernet Media Access Controller (EMAC). The DM646x device supports a single PHY being connected to the EMAC at any given time. The MDIO module is designed to allow almost transparent operation of the MDIO interface with little maintenance from the CPU.

The MDIO module continuously polls 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY device has been detected, the MDIO module reads the MDIO PHY link status register (LINK) to monitor the PHY link state. Link change events are stored in the MDIO module, which can interrupt the CPU. This storing of the events allows the CPU to poll the link status of the PHY device without continuously performing MDIO module accesses. However, when the CPU must access the MDIO module for configuration and negotiation, the MDIO module performs the MDIO read or write operation independent of the CPU. This independent operation allows the processor to poll for completion or interrupt the CPU once the operation has completed.

2.7.1MDIO Module Components

The MDIO module (Figure 10) interfaces to the PHY components through two MDIO pins (MDCLK and MDIO), and to the CPU through the EMAC control module and the configuration bus. The MDIO module consists of the following logical components:

MDIO clock generator

Global PHY detection and link state monitoring

Active PHY monitoring

PHY register user access

Figure 10. MDIO Module Block Diagram

Peripheral

MDIO

 

clock

 

clock

 

 

 

 

generator

MDIO

USERINT

 

 

interface

EMAC

 

 

control

 

 

module

 

 

LINKINT

PHY

PHY

 

monitoring

polling

 

Control

 

Configuration bus

registers

 

 

and logic

 

MDCLK

MDIO

2.7.1.1MDIO Clock Generator

The MDIO clock generator controls the MDIO clock based on a divide-down of the peripheral clock (PLL1/6) in the EMAC control module. The MDIO clock is specified to run up to 2.5 MHZ, although typical operation would be 1.0 MHZ. Since the peripheral clock frequency is variable (PLL1/6), the application software or driver controls the divide-down amount.

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Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x manual Mdio Module Components, Mdio Clock Generator

TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.