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Architecture

Example 2. Receive Buffer Descriptor in C Structure Format

/*

//EMAC Descriptor

//The following is the format of a single buffer descriptor

//on the EMAC.

*/

 

 

 

typedef struct _EMAC_Desc {

 

 

struct _EMAC_Desc *pNext;

/* Pointer to next descriptor in chain

*/

Uint8

*pBuffer;

/* Pointer to data buffer

*/

Uint32

BufOffLen;

/* Buffer Offset(MSW) and Length(LSW)

 

*/

 

 

 

Uint32

PktFlgLen;

/* Packet Flags(MSW) and Length(LSW)

*/

} EMAC_Desc;

 

 

 

/* Packet Flags

 

 

*/

#define EMAC_DSC_FLAG_SOP

0x80000000u

 

#define EMAC_DSC_FLAG_EOP

0x40000000u

 

#define EMAC_DSC_FLAG_OWNER

0x20000000u

 

#define EMAC_DSC_FLAG_EOQ

0x10000000u

 

#define EMAC_DSC_FLAG_TDOWNCMPLT

0x08000000u

 

#define EMAC_DSC_FLAG_PASSCRC

0x04000000u

 

#define EMAC_DSC_FLAG_JABBER

0x02000000u

 

#define EMAC_DSC_FLAG_OVERSIZE

0x01000000u

 

#define EMAC_DSC_FLAG_FRAGMENT

0x00800000u

 

#define EMAC_DSC_FLAG_UNDERSIZED

0x00400000u

 

#define EMAC_DSC_FLAG_CONTROL

0x00200000u

 

#define EMAC_DSC_FLAG_OVERRUN

0x00100000u

 

#define EMAC_DSC_FLAG_CODEERROR

0x00080000u

 

#define EMAC_DSC_FLAG_ALIGNERROR

0x00040000u

 

#define EMAC_DSC_FLAG_CRCERROR

0x00020000u

 

#define EMAC_DSC_FLAG_NOMATCH

0x00010000u

 

2.5.5.3Buffer Offset

This 16-bit field must be initialized to zero by the software application before adding the descriptor to a receive queue.

Whether or not this field is updated depends on the setting of the RXBUFFEROFFSET register. When the offset register is set to a non-zero value, the received packet is written to the packet buffer at an offset given by the value of the register, and this value is also written to the buffer offset field of the descriptor.

When a packet is fragmented over multiple buffers because it does not fit in the first buffer supplied, the buffer offset only applies to the first buffer in the list, which is where the start of packet (SOP) flag is set in the corresponding buffer descriptor. In other words, the buffer offset field is only updated by the EMAC on SOP descriptors.

The range of legal values for the BUFFEROFFSET register is 0 to (Buffer Length – 1) for the smallest value of buffer length for all descriptors in the list.

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Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x manual Example 2. Receive Buffer Descriptor in C Structure Format, Buffer Offset
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TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.
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