List of Figures

 

1

EMAC and MDIO Block Diagram

13

 

2

Ethernet Configuration—MII Connections

15

 

3

Ethernet Configuration—GMII Connections

17

 

4

Ethernet Frame Format

19

 

5

Basic Descriptor Format

20

 

6

Typical Descriptor Linked List

21

 

7

Transmit Buffer Descriptor Format

24

 

8

Receive Buffer Descriptor Format

27

 

9

EMAC Control Module Block Diagram

31

 

10

MDIO Module Block Diagram

34

 

11

EMAC Module Block Diagram

38

 

12

EMAC Control Module Interrupt Logic Diagram

56

 

13

EMAC Control Module Identification and Version Register (CMIDVER)

61

 

14

EMAC Control Module Software Reset Register (CMSOFTRESET)

62

 

15

EMAC Control Module Emulation Control Register (CMEMCONTROL)

62

 

16

EMAC Control Module Interrupt Control Register (CMINTCTRL)

63

 

17

EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN)

64

 

18

EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)

64

 

19

EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)

65

 

20

EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN)

66

 

21

EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT)

67

 

22

EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT)

67

 

23

EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)

68

 

24

EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT)

69

 

25

EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX)

70

 

26

EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX)

70

 

27

MDIO Version Register (VERSION)

71

 

28

MDIO Control Register (CONTROL)

72

 

29

PHY Acknowledge Status Register (ALIVE)

73

 

30

PHY Link Status Register (LINK)

73

 

31

MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)

74

 

32

MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)

75

 

33

MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)

76

 

34

MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

77

 

35

MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)

78

 

36

MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)

79

 

37

MDIO User Access Register 0 (USERACCESS0)

80

 

38

MDIO User PHY Select Register 0 (USERPHYSEL0)

81

 

39

MDIO User Access Register 1 (USERACCESS1)

82

 

40

MDIO User PHY Select Register 1 (USERPHYSEL1)

83

 

41

Transmit Identification and Version Register (TXIDVER)

87

 

42

Transmit Control Register (TXCONTROL)

87

 

43

Transmit Teardown Register (TXTEARDOWN)

88

 

44

Receive Identification and Version Register (RXIDVER)

89

 

45

Receive Control Register (RXCONTROL)

89

 

46

Receive Teardown Register (RXTEARDOWN)

90

 

47

Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)

91

 

48

Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)

92

 

49

Transmit Interrupt Mask Set Register (TXINTMASKSET)

93

 

50

Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)

94

 

51

MAC Input Vector Register (MACINVECTOR)

95

 

52

MAC End Of Interrupt Vector Register (MACEOIVECTOR)

95

6

List of Figures

SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x manual List of Figures
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TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.
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