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Architecture
Table 2. EMAC and MDIO Signals for GMII Interface (continued)
Signal | Type | Description |
MCRS | I | Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in either |
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| transmit or receive. The pin is |
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| necessarily synchronous to MTCLK nor MRCLK. This pin is used in |
MRCLK | I | Receive clock (MRCLK). The receive clock is a continuous clock that provides the timing reference |
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| for receive operations. The MRXD, MRXDV, and MRXER signals are tied to this clock. The clock is |
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| generated by the PHY and is 2.5 MHZ at 10 Mbps operation, 25 MHZ at 100 Mbps operation and |
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| 125 MHZ at 1000 Mbps operation. |
I | Receive data (MRXD). The receive data pins are a collection of 8 data signals comprising 8 bits of | |
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| data. MRDX0 is the |
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| only when MRXDV is asserted. |
MRXDV | I | Receive data valid (MRXDV). The receive data valid signal indicates that the MRXD pins are |
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| generating nibble data for use by the EMAC. It is driven synchronously to MRCLK. |
MRXER | I | Receive error (MRXER). The receive error signal is asserted for one or more MRCLK periods to |
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| indicate that an error was detected in the received frame. This is meaningful only during data |
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| reception when MRXDV is active. |
MDCLK | O | Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module on the |
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| system. It is used to synchronize MDIO data access operations done on the MDIO pin. The |
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| frequency of this clock is controlled by the CLKDIV bits in the MDIO control register (CONTROL). |
MDIO | I/O | Management data input output (MDIO). The MDIO pin drives PHY management data into and out of |
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| the PHY by way of an access frame consisting of start of frame, read/write indication, PHY address, |
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| register address, and data bit cycles. The MDIO pin acts as an output for everything except the data |
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| bit cycles, when the pin acts as an input for read operations. |
18 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) |
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