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Ethernet Media Access Controller (EMAC) Registers

5.50 Network Statistics Registers

 

The EMAC has a set of statistics that record events associated with frame traffic. The statistics values

 

are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL

 

register is set, all statistics registers (see Figure 90) are write-to-decrement. The value written is

 

subtracted from the register value with the result stored in the register. If a value greater than the

 

statistics value is written, then zero is written to the register (writing FFFF FFFFh clears a statistics

 

location). When the GMIIEN bit is cleared, all statistics registers are read/write (normal write direct, so

 

writing 0000 0000h clears a statistics location). All write accesses must be 32-bit accesses.

 

The statistics interrupt (STATPEND) is issued, if enabled, when any statistics value is greater than or

 

equal to 8000 0000h. The statistics interrupt is removed by writing to decrement any statistics value

 

greater than 8000 0000h. The statistics are mapped into internal memory space and are 32-bits wide.

 

All statistics rollover from FFFF FFFFh to 0000 0000h.

 

Figure 90. Statistics Register

31

16

 

COUNT

 

R/WD-0

15

0

 

COUNT

R/WD-0

LEGEND: R/W = Read/Write; WD = Write to decrement; -n= value after reset

5.50.1Good Receive Frames Register (RXGOODFRAMES)

The total number of good frames received on the EMAC. A good frame is defined as having all of the following:

∙Any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode

∙Was of length 64 to RXMAXLEN bytes inclusive

∙Had no CRC error, alignment error, or code error

See Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic.

5.50.2Broadcast Receive Frames Register (RXBCASTFRAMES)

The total number of good broadcast frames received on the EMAC. A good broadcast frame is defined as having all of the following:

∙Any data or MAC control frame that was destined for address FF-FF-FF-FF-FF-FFh only

∙Was of length 64 to RXMAXLEN bytes inclusive

∙Had no CRC error, alignment error, or code error

See Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic.

5.50.3Multicast Receive Frames Register (RXMCASTFRAMES)

The total number of good multicast frames received on the EMAC. A good multicast frame is defined as having all of the following:

∙Any data or MAC control frame that was destined for any multicast address other than FF-FF-FF-FF-FF-FFh

∙Was of length 64 to RXMAXLEN bytes inclusive

∙Had no CRC error, alignment error, or code error

See Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic.

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Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x manual Network Statistics Registers, Good Receive Frames Register Rxgoodframes, Count
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TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

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One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

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