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Architecture

2.15.3MDIO Module Initialization

The MDIO module is used to initially configure and monitor one or more external PHY devices. Other than initializing the software state machine (details on this state machine can be found in the

IEEE 802.3 standard), all that needs to be done for the MDIO module is to enable the MDIO engine and to configure the clock divider. To set the clock divider, supply an MDIO clock of 1 MHZ. For example, since the base clock used is the peripheral clock (PLL1/6), for a processor operating at a PLL frequency of 594 MHZ the divider can be set to 99, with slower MDIO clocks for slower peripheral clock frequencies being perfectly acceptable.

Both the state machine enable and the MDIO clock divider are controlled through the MDIO control register (CONTROL). If none of the potentially connected PHYs require the access preamble, the PREAMBLE bit in CONTROL can also be set to speed up PHY register access. The code for this may appear as in Example 5.

Example 5. MDIO Module Initialization Code

#define PCLK 99

...

/* Enable MDIO and setup divider */

MDIO_REGS->CONTROL = CSL_FMKT( MDIO_CONTROL_ENABLE, YES)

CSL_FMK( MDIO_CONTROL_CLKDIV, PCLK ) ;

If the MDIO module is to operate on an interrupt basis, the interrupts can be enabled at this time using the MDIO user command complete interrupt mask set register (USERINTMASKSET) for register access and the MDIO user PHY select register (USERPHYSELn) if a target PHY is already known.

Once the MDIO state machine has been initialized and enabled, it starts polling all 32 PHY addresses on the MDIO bus, looking for an active PHY. Since it can take up to 50 μs to read one register, it can be some time before the MDIO module provides an accurate representation of whether a PHY is available. Also, a PHY can take up to 3 seconds to negotiate a link. Thus, it is advisable to run the MDIO software off a time-based event rather than polling.

For more information on PHY control registers, see your PHY device documentation.

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Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x manual Example 5. Mdio Module Initialization Code
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TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

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Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.
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