![Manual background](/images/new-backgrounds/123159/123159215x1.webp)
www.ti.com
Ethernet Media Access Controller (EMAC) Registers
5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 66 and described in Table 65.
Figure 66. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
31 |
|
| 16 |
| Reserved |
| |
|
|
| |
15 | 8 | 7 | 0 |
Reserved |
|
| RXFILTERTHRESH |
|
|
LEGEND: R = Read only; R/W = Read/Write;
Table 65. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
RXFILTERTHRESH | Receive filter low threshold. These bits contain the free buffer count threshold value for filtering | ||
|
|
| low priority incoming frames. This field should remain 0, if no filtering is desired. |
5.27 Receive Channel
The receive channel
Figure 67. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
31 |
|
| 16 |
| Reserved |
| |
|
|
| |
15 | 8 | 7 | 0 |
Reserved |
|
| RXnFLOWTHRESH |
|
|
LEGEND: R = Read only; R/W = Read/Write;
Table 66. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)
Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
RXnFLOWTHRESH | Receive flow threshold. These bits contain the threshold value for issuing flow control on | ||
|
|
| incoming frames for channel n (when enabled). |
108 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) |
Submit Documentation Feedback