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Ethernet Media Access Controller (EMAC) Registers
5.22 Receive Unicast Enable Set Register (RXUNICASTSET)
The receive unicast enable set register (RXUNICASTSET) is shown in Figure 62 and described in Table 61.
| Figure 62. Receive Unicast Enable Set Register (RXUNICASTSET) |
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31 |
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| 16 |
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| Reserved |
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15 |
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| 8 |
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| Reserved |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXCH7EN | RXCH6EN | RXCH5EN | RXCH4EN | RXCH3EN | RXCH2EN | RXCH1EN | RXCH0EN |
LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect;
Table 61. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
7 | RXCH7EN | Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
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| May be read. |
6 | RXCH6EN | Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
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| May be read. |
5 | RXCH5EN | Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
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| May be read. |
4 | RXCH4EN | Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
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| May be read. |
3 | RXCH3EN | Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
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| May be read. |
2 | RXCH2EN | Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
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| May be read. |
1 | RXCH1EN | Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
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| May be read. |
0 | RXCH0EN | Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. | |
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| May be read. |
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | 105 | |
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