4.3

PHY Acknowledge Status Register (ALIVE)

73

 

 

4.4

PHY Link Status Register (LINK)

73

 

 

4.5

MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)

74

 

 

4.6

MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)

75

 

 

4.7

MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)

76

 

 

4.8

MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

77

 

 

4.9

MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)

78

 

 

4.10

MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)

79

 

 

4.11

MDIO User Access Register 0 (USERACCESS0)

80

 

 

4.12

MDIO User PHY Select Register 0 (USERPHYSEL0)

81

 

 

4.13

MDIO User Access Register 1 (USERACCESS1)

82

 

 

4.14

MDIO User PHY Select Register 1 (USERPHYSEL1)

83

 

5

Ethernet Media Access Controller (EMAC) Registers

84

 

 

5.1

Transmit Identification and Version Register (TXIDVER)

87

 

 

5.2

Transmit Control Register (TXCONTROL)

87

 

 

5.3

Transmit Teardown Register (TXTEARDOWN)

88

 

 

5.4

Receive Identification and Version Register (RXIDVER)

89

 

 

5.5

Receive Control Register (RXCONTROL)

89

 

 

5.6

Receive Teardown Register (RXTEARDOWN)

90

 

 

5.7

Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)

91

 

 

5.8

Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)

92

 

 

5.9

Transmit Interrupt Mask Set Register (TXINTMASKSET)

93

 

 

5.10

Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)

94

 

 

5.11

MAC Input Vector Register (MACINVECTOR)

95

 

 

5.12

MAC End Of Interrupt Vector Register (MACEOIVECTOR)

95

 

 

5.13

Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)

96

 

 

5.14

Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)

97

 

 

5.15

Receive Interrupt Mask Set Register (RXINTMASKSET)

98

 

 

5.16

Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

99

 

 

5.17

MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)

100

 

 

5.18

MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)

100

 

 

5.19

MAC Interrupt Mask Set Register (MACINTMASKSET)

101

 

 

5.20

MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

101

 

 

5.21

Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)

102

 

 

5.22

Receive Unicast Enable Set Register (RXUNICASTSET)

105

 

 

5.23

Receive Unicast Clear Register (RXUNICASTCLEAR)

106

 

 

5.24

Receive Maximum Length Register (RXMAXLEN)

107

 

 

5.25

Receive Buffer Offset Register (RXBUFFEROFFSET)

107

 

 

5.26

Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)

108

 

 

5.27

Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH)

108

 

 

5.28

Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)

109

 

 

5.29

MAC Control Register (MACCONTROL)

110

 

 

5.30

MAC Status Register (MACSTATUS)

112

 

 

5.31

Emulation Control Register (EMCONTROL)

114

 

 

5.32

FIFO Control Register (FIFOCONTROL)

114

 

 

5.33

MAC Configuration Register (MACCONFIG)

115

 

 

5.34

Soft Reset Register (SOFTRESET)

115

 

 

5.35

MAC Source Address Low Bytes Register (MACSRCADDRLO)

116

4

Contents

SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x manual Receive Unicast Clear Register Rxunicastclear
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TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.
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