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Ethernet Media Access Controller (EMAC) Registers
5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 54 and described in Table 53.
| Figure 54. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) |
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31 |
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| 16 |
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| Reserved |
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15 |
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| 8 |
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| Reserved |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX7PEND | RX6PEND | RX5PEND | RX4PEND | RX3PEND | RX2PEND | RX1PEND | RX0PEND |
LEGEND: R = Read only;
Table 53. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
7 | RX7PEND | RX7PEND masked interrupt read | |
6 | RX6PEND | RX6PEND masked interrupt read | |
5 | RX5PEND | RX5PEND masked interrupt read | |
4 | RX4PEND | RX4PEND masked interrupt read | |
3 | RX3PEND | RX3PEND masked interrupt read | |
2 | RX2PEND | RX2PEND masked interrupt read | |
1 | RX1PEND | RX1PEND masked interrupt read | |
0 | RX0PEND | RX0PEND masked interrupt read |
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | 97 | |
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