www.ti.com

Ethernet Media Access Controller (EMAC) Registers

Table 39. Ethernet Media Access Controller (EMAC) Registers (continued)

Offset

Acronym

Register Description

Section

678h

RX6CP

Receive Channel 6 Completion Pointer Register

Section 5.49

67Ch

RX7CP

Receive Channel 7 Completion Pointer Register

Section 5.49

 

 

Network Statistics Registers

 

200h

RXGOODFRAMES

Good Receive Frames Register

Section 5.50.1

204h

RXBCASTFRAMES

Broadcast Receive Frames Register

Section 5.50.2

208h

RXMCASTFRAMES

Multicast Receive Frames Register

Section 5.50.3

20Ch

RXPAUSEFRAMES

Pause Receive Frames Register

Section 5.50.4

210h

RXCRCERRORS

Receive CRC Errors Register

Section 5.50.5

214h

RXALIGNCODEERRORS

Receive Alignment/Code Errors Register

Section 5.50.6

218h

RXOVERSIZED

Receive Oversized Frames Register

Section 5.50.7

21Ch

RXJABBER

Receive Jabber Frames Register

Section 5.50.8

220h

RXUNDERSIZED

Receive Undersized Frames Register

Section 5.50.9

224h

RXFRAGMENTS

Receive Frame Fragments Register

Section 5.50.10

228h

RXFILTERED

Filtered Receive Frames Register

Section 5.50.11

22Ch

RXQOSFILTERED

Receive QOS Filtered Frames Register

Section 5.50.12

230h

RXOCTETS

Receive Octet Frames Register

Section 5.50.13

234h

TXGOODFRAMES

Good Transmit Frames Register

Section 5.50.14

238h

TXBCASTFRAMES

Broadcast Transmit Frames Register

Section 5.50.15

23Ch

TXMCASTFRAMES

Multicast Transmit Frames Register

Section 5.50.16

240h

TXPAUSEFRAMES

Pause Transmit Frames Register

Section 5.50.17

244h

TXDEFERRED

Deferred Transmit Frames Register

Section 5.50.18

248h

TXCOLLISION

Transmit Collision Frames Register

Section 5.50.19

24Ch

TXSINGLECOLL

Transmit Single Collision Frames Register

Section 5.50.20

250h

TXMULTICOLL

Transmit Multiple Collision Frames Register

Section 5.50.21

254h

TXEXCESSIVECOLL

Transmit Excessive Collision Frames Register

Section 5.50.22

258h

TXLATECOLL

Transmit Late Collision Frames Register

Section 5.50.23

25Ch

TXUNDERRUN

Transmit Underrun Error Register

Section 5.50.24

260h

TXCARRIERSENSE

Transmit Carrier Sense Errors Register

Section 5.50.25

264h

TXOCTETS

Transmit Octet Frames Register

Section 5.50.26

268h

FRAME64

Transmit and Receive 64 Octet Frames Register

Section 5.50.27

26Ch

FRAME65T127

Transmit and Receive 65 to 127 Octet Frames Register

Section 5.50.28

270h

FRAME128T255

Transmit and Receive 128 to 255 Octet Frames Register

Section 5.50.29

274h

FRAME256T511

Transmit and Receive 256 to 511 Octet Frames Register

Section 5.50.30

278h

FRAME512T1023

Transmit and Receive 512 to 1023 Octet Frames Register

Section 5.50.31

27Ch

FRAME1024TUP

Transmit and Receive 1024 to RXMAXLEN Octet Frames Register

Section 5.50.32

280h

NETOCTETS

Network Octet Frames Register

Section 5.50.33

284h

RXSOFOVERRUNS

Receive FIFO or DMA Start of Frame Overruns Register

Section 5.50.34

288h

RXMOFOVERRUNS

Receive FIFO or DMA Middle of Frame Overruns Register

Section 5.50.35

28Ch

RXDMAOVERRUNS

Receive DMA Overruns Register

Section 5.50.36

86

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRUEQ6–December 2007

 

 

Submit Documentation Feedback

Page 86
Image 86
Texas Instruments TMS320DM646x manual RX6CP, RX7CP, Rxgoodframes, Rxbcastframes, Rxmcastframes, Rxpauseframes, Rxcrcerrors

TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.