Manuals / Texas Instruments / Computer Equipment / Computer Hardware

Texas Instruments TMS320DM646x manual MAC Interrupt Mask Set Register MACINTMASKSET

Models: TMS320DM646x

1 135

Download 135 pages 29.86 Kb

Page 101

5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)

www.ti.com

Ethernet Media Access Controller (EMAC) Registers

5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)

The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 59 and described in Table 58.

Figure 59. MAC Interrupt Mask Set Register (MACINTMASKSET)

31			16
	Reserved
	R-0
15	2	1	0
Reserved		HOSTMASK	STATMASK
R-0		R/W1S-0	R/W1S-0

LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n= value after reset

Table 58. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions

Bit	Field	Value	Description
31-2	Reserved	0	Reserved
1	HOSTMASK	0-1	Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
0	STATMASK	0-1	Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.

5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 60 and described in Table 59.

Figure 60. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)

31			16
	Reserved
	R-0
15	2	1	0
Reserved		HOSTMASK	STATMASK
R-0		R/W1C-0	R/W1C-0

LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n= value after reset

Table 59. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions

Bit	Field	Value	Description
31-2	Reserved	0	Reserved
1	HOSTMASK	0-1	Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
0	STATMASK	0-1	Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

SPRUEQ6–December 2007	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	101
Submit Documentation Feedback

Image 101

Texas Instruments TMS320DM646x manual MAC Interrupt Mask Set Register MACINTMASKSET

Contents

Management Data Input/Output MDIO Module TMS320DM646x DMSoC Ethernet Media Access Controller EMACUsers Guide Submit Documentation Feedback SPRUEQ6-DecemberContents PHY Acknowledge Status Register ALIVE MAC Hash Address Register 1 MACHASH1 List of Figures List of FiguresReceive Interrupt Mask Set Register RXINTMASKSET List of Tables MAC Control Register MACCONTROL Field Descriptions Soft Reset Register SOFTRESET Field DescriptionsMAC Status Register MACSTATUS Field Descriptions FIFO Control Register FIFOCONTROL Field DescriptionsPreface Read This FirstAbout This Manual Notational ConventionsRead This First Related Documentation From Texas Instruments1.2 Features Users Guide1 Introduction 1.1 Purpose of the PeripheralFigure 1. EMAC and MDIO Block Diagram 1.3 Functional Block Diagram2 Architecture 1.4 Industry Standards Compliance Statement2.1 Clock Control 2.1.1 MII ClockingFigure 2. Ethernet Configuration-MII Connections 2.3 Signal Descriptions2.2 Memory Map 2.3.1 Media Independent Interface MII ConnectionsSignal Table 1. EMAC and MDIO Signals for MII InterfaceArchitecture TypeTable 2. EMAC and MDIO Signals for GMII Interface Figure 3. Ethernet Configuration-GMII Connections2.3.2 Gigabit Media Independent Interface GMII Connections MTCLK GMTCLK RFTCLK MTXD7−0 MTXEN MCOL MCRS MRCLK MRXD7−0 MRXDV MRXERSignal Table 2. EMAC and MDIO Signals for GMII Interface continuedArchitecture Type2.4.1 Ethernet Frame Format 2.4 Ethernet Protocol OverviewFigure 4. Ethernet Frame Format Table 3. Ethernet Frame Description2.5 Programming Interface 2.4.2 Ethernet’s Multiple Access Protocol2.5.1 Packet Buffer Descriptors Figure 5. Basic Descriptor FormatFigure 6. Typical Descriptor Linked List Table 4. Basic Descriptor Description2.5.2 Transmit and Receive Descriptor Queues 2.5.3 Transmit and Receive EMAC Interrupts Figure 7. Transmit Buffer Descriptor Format 2.5.4 Transmit Buffer Descriptor FormatExample 1. Transmit Buffer Descriptor in C Structure Format Architecture2.5.4.2 Buffer Pointer 2.5.4.1 Next Descriptor Pointer2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length2.5.4.8 Ownership OWNER Flag 2.5.4.7 End of Packet EOP Flag2.5.4.9 End of Queue EOQ Flag 2.5.4.10 Teardown Complete TDOWNCMPLT Flag2.5.5.1 Next Descriptor Pointer 2.5.5 Receive Buffer Descriptor Format2.5.5.2 Buffer Pointer Figure 8. Receive Buffer Descriptor Format2.5.5.3 Buffer Offset Example 2. Receive Buffer Descriptor in C Structure Format2.5.5.5 Packet Length 2.5.5.4 Buffer Length2.5.5.6 Start of Packet SOP Flag 2.5.5.7 End of Packet EOP Flag2.5.5.19 Alignment Error ALIGNERROR Flag 2.5.5.18 Code Error CODEERROR Flag2.5.5.20 CRC Error CRCERROR Flag 2.5.5.10 Teardown Complete TDOWNCMPLT Flag2.6 EMAC Control Module Figure 9. EMAC Control Module Block Diagram2.5.5.21 No Match NOMATCH Flag 2.6.1 Internal MemoryTable 5. EMAC Control Module Interrupts 2.6.3 Interrupt Control2.6.3.1 Transmit Pulse Interrupt 2.6.3.2 Receive Pulse Interrupt2.6.4 Interrupt Pacing 2.6.3.3 Receive Threshold Pulse Interrupt2.6.3.4 Miscellaneous Pulse Interrupt 2.7 MDIO Module Figure 10. MDIO Module Block Diagram2.7.1 MDIO Module Components 2.7.1.1 MDIO Clock Generator2.7.1.2 Global PHY Detection and Link State Monitoring 2.7.1.4 PHY Register User Access2.7.1.3 Active PHY Monitoring 2.7.2 MDIO Module Operational Overview2.7.2.3 Reading Data From a PHY Register 2.7.2.1 Initializing the MDIO Module2.7.2.2 Writing Data To a PHY Register Example 3. MDIO Register Access Macros 2.7.2.4 Example of MDIO Register Access Code2.8 EMAC Module Figure 11. EMAC Module Block Diagram2.8.1 EMAC Module Components 2.8.1.1 Receive DMA Engine2.8.1.3 MAC Receiver 2.8.1.12 Clock and Reset Logic2.8.1.4 Receive Address 2.8.1.5 Transmit DMA Engine2.8.2 EMAC Module Operational Overview 2.9.1 Data Reception 2.9 Media Independent Interface MII2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval2.9.1.3.2 IEEE 802.3x-Based Receive Buffer Flow Control 2.9.1.3.1 Collision-Based Receive Buffer Flow Control2.9.2.1 Transmit Control 2.9.2 Data Transmission2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization APO2.9.2.7 Speed, Duplex, and Pause Frame Support 2.9.2.6 Transmit Flow Control2.10.2 Receive Channel Enabling 2.10.1 Receive DMA Host Configuration2.10 Packet Receive Operation 2.10.5 Host Free Buffer Tracking 2.10.3 Receive Address Matching2.10.4 Hardware Receive QOS Support 2.10.7 Receive Frame Classification 2.10.6 Receive Channel TeardownTable 6. Receive Frame Treatment Summary 2.10.8 Promiscuous Receive ModeRXCAFEN RXCEFENTable 7. Middle of Frame Overrun Treatment Table 6. Receive Frame Treatment Summary continued2.10.9 Receive Overrun 2.11 Packet Transmit Operation 2.11.1 Transmit DMA Host Configuration2.12 Receive and Transmit Latency 2.11.2 Transmit Channel Teardown2.13 Transfer Node Priority 2.14 Reset Considerations2.14.1 Software Reset Considerations 2.15 Initialization 2.14.2 Hardware Reset Considerations2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.2 EMAC Control Module InitializationSubmit Documentation Feedback Example 4. EMAC Control Module Initialization CodeArchitecture Example 5. MDIO Module Initialization Code 2.15.3 MDIO Module Initialization2.15.4 EMAC Module Initialization 2.16 Interrupt Support Figure 12. EMAC Control Module Interrupt Logic Diagram2.16.1 EMAC Module Interrupt Events and Requests 2.16.1.1 Receive Threshold Interrupts2.16.1.3 Receive Packet Completion Interrupts 2.16.1.2 Transmit Packet Completion Interrupts2.16.1.4 Statistics Interrupt 2.16.1.5 Host Error Interrupt2.16.2 MDIO Module Interrupt Events and Requests 2.16.2.2 User Access Completion Interrupt2.16.2.1 Link Change Interrupt 2.16.3 Proper Interrupt ProcessingTable 8. Emulation Control 2.17 Power Management2.18 Emulation Considerations 3.1 EMAC Control Module Identification and Version Register CMIDVER 3 EMAC Control Module RegistersTable 9. EMAC Control Module Registers Field DescriptionsFigure 14. EMAC Control Module Software Reset Register CMSOFTRESET 3.2 EMAC Control Module Software Reset Register CMSOFTRESET3.3 EMAC Control Module Emulation Control Register CMEMCONTROL Figure 15. EMAC Control Module Emulation Control Register CMEMCONTROLFigure 16. EMAC Control Module Interrupt Control Register CMINTCTRL 3.4 EMAC Control Module Interrupt Control Register CMINTCTRLTable 13. EMAC Control Module Interrupt Control Register CMINTCTRL Field Descriptions3.6 EMAC Control Module Receive Interrupt Enable Register CMRXINTEN 3.5 EMAC Control Module Receive Threshold Interrupt Enable RegisterCMRXTHRESHINTEN CMRXTHRESHINTENField Descriptions 3.7 EMAC Control Module Transmit Interrupt Enable Register CMTXINTENField Descriptions CMRXTHRESHINTSTAT 3.9 EMAC Control Module Receive Threshold Interrupt Status RegisterCMRXTHRESHINTSTAT CMRXTHRESHINTSTAT Field DescriptionsField Descriptions Field Descriptions 3.13 EMAC Control Module Receive Interrupts per Millisecond Register CMRXINTMAX 4.1 MDIO Version Register VERSION 4 MDIO RegistersTable 24. Management Data Input/Output MDIO Registers Figure 27. MDIO Version Register VERSIONFigure 28. MDIO Control Register CONTROL 4.2 MDIO Control Register CONTROLTable 26. MDIO Control Register CONTROL Field Descriptions MDIO Registers4.4 PHY Link Status Register LINK 4.3 PHY Acknowledge Status Register ALIVEFigure 29. PHY Acknowledge Status Register ALIVE Table 27. PHY Acknowledge Status Register ALIVE Field DescriptionsField Descriptions 4.5 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAWField Descriptions 4.6 MDIO Link Status Change Interrupt Masked Register LINKINTMASKEDField Descriptions 4.7 MDIO User Command Complete Interrupt Unmasked Register USERINTRAWField Descriptions Field Descriptions Figure 36 and described in Table Figure 36. MDIO User Command Complete Interrupt Mask Clear RegisterUSERINTMASKCLEAR Field DescriptionsFigure 37. MDIO User Access Register 0 USERACCESS0 4.11 MDIO User Access Register 0 USERACCESS0Table 35. MDIO User Access Register 0 USERACCESS0 Field Descriptions MDIO RegistersFigure 38. MDIO User PHY Select Register 0 USERPHYSEL0 4.12 MDIO User PHY Select Register 0 USERPHYSEL0MDIO Registers FieldFigure 39. MDIO User Access Register 1 USERACCESS1 4.13 MDIO User Access Register 1 USERACCESS1Table 37. MDIO User Access Register 1 USERACCESS1 Field Descriptions MDIO RegistersFigure 40. MDIO User PHY Select Register 1 USERPHYSEL1 4.14 MDIO User PHY Select Register 1 USERPHYSEL1MDIO Registers FieldTable 39. Ethernet Media Access Controller EMAC Registers 5 Ethernet Media Access Controller EMAC RegistersEthernet Media Access Controller EMAC Registers AcronymEthernet Media Access Controller EMAC Registers Table 39. Ethernet Media Access Controller EMAC Registers continuedOffset AcronymEthernet Media Access Controller EMAC Registers Table 39. Ethernet Media Access Controller EMAC Registers continuedOffset Acronym5.2 Transmit Control Register TXCONTROL 5.1 Transmit Identification and Version Register TXIDVERFigure 41. Transmit Identification and Version Register TXIDVER Figure 42. Transmit Control Register TXCONTROL5.3 Transmit Teardown Register TXTEARDOWN Ethernet Media Access Controller EMAC RegistersFigure 43. Transmit Teardown Register TXTEARDOWN Table 42. Transmit Teardown Register TXTEARDOWN Field Descriptions5.5 Receive Control Register RXCONTROL 5.4 Receive Identification and Version Register RXIDVERFigure 44. Receive Identification and Version Register RXIDVER Figure 45. Receive Control Register RXCONTROL5.6 Receive Teardown Register RXTEARDOWN Ethernet Media Access Controller EMAC RegistersFigure 46. Receive Teardown Register RXTEARDOWN Table 45. Receive Teardown Register RXTEARDOWN Field Descriptions5.7 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Ethernet Media Access Controller EMAC RegistersFigure 47. Transmit Interrupt Status Unmasked Register TXINTSTATRAW Field5.8 Transmit Interrupt Status Masked Register TXINTSTATMASKED Ethernet Media Access Controller EMAC RegistersFigure 48. Transmit Interrupt Status Masked Register TXINTSTATMASKED Field5.9 Transmit Interrupt Mask Set Register TXINTMASKSET Ethernet Media Access Controller EMAC RegistersFigure 49. Transmit Interrupt Mask Set Register TXINTMASKSET Field5.10 Transmit Interrupt Mask Clear Register TXINTMASKCLEAR Ethernet Media Access Controller EMAC RegistersFigure 50. Transmit Interrupt Mask Clear Register TXINTMASKCLEAR Field5.12 MAC End Of Interrupt Vector Register MACEOIVECTOR 5.11 MAC Input Vector Register MACINVECTORFigure 51. MAC Input Vector Register MACINVECTOR Table 50. MAC Input Vector Register MACINVECTOR Field Descriptions5.13 Receive Interrupt Status Unmasked Register RXINTSTATRAW Ethernet Media Access Controller EMAC RegistersFigure 53. Receive Interrupt Status Unmasked Register RXINTSTATRAW Field5.14 Receive Interrupt Status Masked Register RXINTSTATMASKED Ethernet Media Access Controller EMAC RegistersFigure 54. Receive Interrupt Status Masked Register RXINTSTATMASKED Field5.15 Receive Interrupt Mask Set Register RXINTMASKSET Ethernet Media Access Controller EMAC RegistersFigure 55. Receive Interrupt Mask Set Register RXINTMASKSET Field5.16 Receive Interrupt Mask Clear Register RXINTMASKCLEAR Ethernet Media Access Controller EMAC RegistersFigure 56. Receive Interrupt Mask Clear Register RXINTMASKCLEAR Field5.18 MAC Interrupt Status Masked Register MACINTSTATMASKED 5.17 MAC Interrupt Status Unmasked Register MACINTSTATRAWFigure 57. MAC Interrupt Status Unmasked Register MACINTSTATRAW Figure 58. MAC Interrupt Status Masked Register MACINTSTATMASKED5.20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR 5.19 MAC Interrupt Mask Set Register MACINTMASKSETFigure 59. MAC Interrupt Mask Set Register MACINTMASKSET Figure 60. MAC Interrupt Mask Clear Register MACINTMASKCLEARField Descriptions Field Descriptions continued Ethernet Media Access Controller EMAC RegistersField ValueField Descriptions continued Ethernet Media Access Controller EMAC RegistersField ValueFigure 62. Receive Unicast Enable Set Register RXUNICASTSET 5.22 Receive Unicast Enable Set Register RXUNICASTSETEthernet Media Access Controller EMAC Registers Field5.23 Receive Unicast Clear Register RXUNICASTCLEAR Ethernet Media Access Controller EMAC RegistersFigure 63. Receive Unicast Clear Register RXUNICASTCLEAR Field5.25 Receive Buffer Offset Register RXBUFFEROFFSET 5.24 Receive Maximum Length Register RXMAXLENFigure 64. Receive Maximum Length Register RXMAXLEN Table 63. Receive Maximum Length Register RXMAXLEN Field DescriptionsField Descriptions Field Descriptionsdescribed in Table 5.28 Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER5.29 MAC Control Register MACCONTROL Ethernet Media Access Controller EMAC RegistersFigure 69. MAC Control Register MACCONTROL Table 68. MAC Control Register MACCONTROL Field DescriptionsDescription FieldSubmit Documentation Feedback Value5.30 MAC Status Register MACSTATUS Ethernet Media Access Controller EMAC RegistersFigure 70. MAC Status Register MACSTATUS Table 69. MAC Status Register MACSTATUS Field DescriptionsField Table 69. MAC Status Register MACSTATUS Field Descriptions continuedValue Description5.32 FIFO Control Register FIFOCONTROL 5.31 Emulation Control Register EMCONTROLFigure 71. Emulation Control Register EMCONTROL Table 70. Emulation Control Register EMCONTROL Field Descriptions5.34 Soft Reset Register SOFTRESET 5.33 MAC Configuration Register MACCONFIGFigure 73. MAC Configuration Register MACCONFIG Table 72. MAC Configuration Register MACCONFIG Field Descriptions5.36 MAC Source Address High Bytes Register MACSRCADDRHI 5.35 MAC Source Address Low Bytes Register MACSRCADDRLOFigure 75. MAC Source Address Low Bytes Register MACSRCADDRLO Figure 76. MAC Source Address High Bytes Register MACSRCADDRHI5.38 MAC Hash Address Register 2 MACHASH2 5.37 MAC Hash Address Register 1 MACHASH1Figure 77. MAC Hash Address Register 1 MACHASH1 Table 76. MAC Hash Address Register 1 MACHASH1 Field Descriptions5.40 Transmit Pacing Algorithm Test Register TPACETEST 5.39 Back Off Test Register BOFFTESTFigure 79. Back Off Random Number Generator Test Register BOFFTEST Table 78. Back Off Test Register BOFFTEST Field Descriptions5.42 Transmit Pause Timer Register TXPAUSE 5.41 Receive Pause Timer Register RXPAUSEFigure 81. Receive Pause Timer Register RXPAUSE Table 80. Receive Pause Timer Register RXPAUSE Field Descriptions5.43 MAC Address Low Bytes Register MACADDRLO Ethernet Media Access Controller EMAC RegistersFigure 83. MAC Address Low Bytes Register MACADDRLO Table 82. MAC Address Low Bytes Register MACADDRLO Field Descriptions5.45 MAC Index Register MACINDEX 5.44 MAC Address High Bytes Register MACADDRHIFigure 84. MAC Address High Bytes Register MACADDRHI Figure 85. MAC Index Register MACINDEX5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register RXnHDP 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register TXnHDPField Descriptions Field Descriptions5.49 Receive Channel 0-7 Completion Pointer Register RXnCP 5.48 Transmit Channel 0-7 Completion Pointer Register TXnCPFigure 88. Transmit Channel n Completion Pointer Register TX nCP Figure 89. Receive Channel n Completion Pointer Register RX nCPFigure 90. Statistics Register 5.50 Network Statistics Registers5.50.1 Good Receive Frames Register RXGOODFRAMES 5.50.2 Broadcast Receive Frames Register RXBCASTFRAMES5.50.6 Receive Alignment/Code Errors Register RXALIGNCODEERRORS 5.50.5 Receive CRC Errors Register RXCRCERRORS5.50.4 Pause Receive Frames Register RXPAUSEFRAMES 5.50.7 Receive Oversized Frames Register RXOVERSIZED5.50.9 Receive Undersized Frames Register RXUNDERSIZED 5.50.8 Receive Jabber Frames Register RXJABBER5.50.10 Receive Frame Fragments Register RXFRAGMENTS 5.50.11 Filtered Receive Frames Register RXFILTERED5.50.13 Receive Octet Frames Register RXOCTETS 5.50.12 Receive QOS Filtered Frames Register RXQOSFILTERED5.50.14 Good Transmit Frames Register TXGOODFRAMES 5.50.15 Broadcast Transmit Frames Register TXBCASTFRAMES5.50.17 Pause Transmit Frames Register TXPAUSEFRAMES 5.50.16 Multicast Transmit Frames Register TXMCASTFRAMES5.50.18 Deferred Transmit Frames Register TXDEFERRED 5.50.19 Transmit Collision Frames Register TXCOLLISION5.50.25 Transmit Carrier Sense Errors Register TXCARRIERSENSE 5.50.24 Transmit Underrun Error Register TXUNDERRUN5.50.21 Transmit Multiple Collision Frames Register TXMULTICOLL 5.50.22 Transmit Excessive Collision Frames Register TXEXCESSIVECOLL5.50.27 Transmit and Receive 64 Octet Frames Register FRAME64 5.50.26 Transmit Octet Frames Register TXOCTETS5.50.33 Network Octet Frames Register NETOCTETS 5.50.36 Receive DMA Overruns Register RXDMAOVERRUNS Ethernet Media Access Controller EMAC RegistersAppendix A Appendix A GlossaryTable A-1. Physical Layer Definitions IMPORTANT NOTICE power.ti.comProducts Applications