www.ti.com

Ethernet Media Access Controller (EMAC) Registers

5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)

The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 61 and described in Table 60.

Figure 61. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)

31

30

29

28

27

 

25

24

Reserved

RXPASSCRC

RXQOSEN

RXNOCHAIN

 

Reserved

 

RXCMFEN

R-0

R/W-0

R/W-0

R/W-0

 

R-0

 

R/W-0

23

22

21

20

19

18

 

16

RXCSFEN

RXCEFEN

RXCAFEN

Reserved

 

 

RXPROMCH

 

R/W-0

R/W-0

R/W-0

R-0

 

 

R/W-0

 

15

14

13

12

11

10

 

8

Reserved

RXBROADEN

Reserved

 

 

RXBROADCH

 

 

R-0

R/W-0

R-0

 

 

R/W-0

 

7

6

5

4

3

2

 

0

Reserved

RXMULTEN

Reserved

 

 

RXMULTCH

 

 

R-0

R/W-0

R-0

 

 

R/W-0

 

LEGEND: R = Read only; R/W = Read/Write; -n= value after reset

Table 60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)

Field Descriptions

Bit

Field

Value

Description

31

Reserved

0

Reserved

30

RXPASSCRC

 

Pass receive CRC enable bit

 

 

0

Received CRC is discarded for all channels and is not included in the buffer descriptor packet

 

 

 

length field.

 

 

1

Received CRC is transferred to memory for all channels and is included in the buffer descriptor

 

 

 

packet length.

29

RXQOSEN

 

Receive quality of service enable bit

 

 

0

Receive QOS is disabled.

 

 

1

Receive QOS is enabled.

28

RXNOCHAIN

 

Receive no buffer chaining bit

 

 

0

Received frames can span multiple buffers.

 

 

1

The Receive DMA controller transfers each frame into a single buffer, regardless of the frame or

 

 

 

buffer size. All remaining frame data after the first buffer is discarded. The buffer descriptor buffer

 

 

 

length field will contain the entire frame byte count (up to 65535 bytes).

27-25

Reserved

0

Reserved

24

RXCMFEN

 

Receive copy MAC control frames enable bit. Enables MAC control frames to be transferred to

 

 

 

memory. MAC control frames are normally acted upon (if enabled), but not copied to memory. MAC

 

 

 

control frames that are pause frames will be acted upon if enabled in MACCONTROL, regardless of

 

 

 

the value of RXCMFEN. Frames transferred to memory due to RXCMFEN will have the CONTROL

 

 

 

bit set in their EOP buffer descriptor.

 

 

0

MAC control frames are filtered (but acted upon if enabled).

 

 

1

MAC control frames are transferred to memory.

23

RXCSFEN

 

Receive copy short frames enable bit. Enables frames or fragments shorter than 64 bytes to be

 

 

 

copied to memory. Frames transferred to memory due to RXCSFEN will have the FRAGMENT or

 

 

 

UNDERSIZE bit set in their EOP buffer descriptor. Fragments are short frames that contain CRC /

 

 

 

align / code errors and undersized are short frames without errors.

 

 

0

Short frames are filtered.

 

 

1

Short frames are transferred to memory.

102

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRUEQ6–December 2007

Submit Documentation Feedback

Page 102
Image 102
Texas Instruments TMS320DM646x manual Rxpasscrc Rxqosen Rxnochain, Rxcmfen, Rxcsfen Rxcefen Rxcafen, Rxpromch, Rxbroaden

TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

Power management is a primary focus in the design of the TMS320DM646x series. The processors are built to operate efficiently with minimal power consumption, making them suitable for portable and battery-operated devices. The low power characteristics do not compromise performance, enabling high computational capabilities while maintaining energy efficiency.

Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.