Texas Instruments TMS320DM646x manual Transfer Node Priority, Reset Considerations

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Architecture

Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a 64-byte cell on the wire (0.512 ms in 1 Gbps mode, 5.12 ms in 100 Mbps mode, or 51.2ms in 10 Mbps mode). The latency time includes any required buffer descriptor reads for the cell data.

Latency to descriptor RAM is low because RAM is local to the EMAC, as it is part of the EMAC control module.

2.13 Transfer Node Priority

The DM646x device contains a chip-level register, master priority register (MSTPRI), that is used to set the priority of the transfer node used in issuing memory transfer requests to system memory.

Although the EMAC has internal FIFOs to help alleviate memory transfer arbitration problems, the average transfer rate of data read and written by the EMAC to internal or external processor memory must be at least that of the Ethernet wire rate. In addition, the internal FIFO system can not withstand a single memory latency event greater than the time it takes to fill or empty a TXCELLTHRESH number of internal 64-byte FIFO cells.

For 100 Mbps operation, these restrictions translate into the following rules:

∙The short-term average, each 64-byte memory read/write request from the EMAC must be serviced in no more than 5.12 μs.

∙Any single latency event in request servicing can be no longer than (5.12 × TXCELLTHRESH) μs.

Bits 0-2 of the second chip-level master priority register (MSTPRI1) are used to set the transfer node priority within the Switched Central Resource (SCR5) for the EMAC master peripheral.

A value of 000b has the highest priority, while 111b has the lowest priority. The default priority assigned to the EMAC is 100b. It is important to have a balance between all peripherals. In most cases, the default priorities will not need adjustment. For more information on the master peripherals priorities, see the device-specific data manual.

2.14 Reset Considerations

2.14.1Software Reset Considerations

Peripheral clock and reset control is done through the Power and Sleep Controller (PSC) module included with the device. For more on how the EMAC, MDIO, and EMAC control module are disabled or placed in reset at runtime from the registers located in the PSC module, see Section 2.17.

Note: For proper operation, both the EMAC and EMAC control module must be reset in the following sequence. First, the soft reset of the EMAC module should be commanded. After the reset takes effect (verified by reading back SOFTRESET), the soft reset of the EMAC control module should be commanded.

Within the peripheral there are two controls to separately reset the EMAC and the EMAC control module.

∙The EMAC component of the Ethernet MAC peripheral can be placed in a reset state by writing to the soft reset register (SOFTRESET). Writing a 1 to the SOFTRESET bit, causes the EMAC logic to be reset and the register values to be set to their default values. Software reset occurs when the receive and transmit DMA controllers are in an idle state to avoid locking up the configuration bus; it is the responsibility of the software to verify that there are no pending frames to be transferred. After writing a 1 to the SOFTRESET bit, it may be polled to determine if the reset has occurred. If a 1 is read, the reset has not yet occurred; if a 0 is read, then a reset has occurred.

∙The EMAC control module software reset register (CMSOFTRESET) is used to place the EMAC control module logic in soft reset. This resets the control logic, the EMAC registers, as well as, the EMAC control module 8KB internal memory that may be used for storing the transfer descriptors.

After a software reset operation, all the EMAC registers need to be reinitialized for proper data transmission.

Unlike the EMAC module, the MDIO and EMAC control modules cannot be placed in reset from a register inside their memory map.

SPRUEQ6–December 2007 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 51

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