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MDIO Registers
4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in
Figure 36 and described in Table 34. |
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Figure 36. MDIO User Command Complete Interrupt Mask Clear Register |
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(USERINTMASKCLEAR) |
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31 |
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| 16 |
Reserved |
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15 | 2 | 1 | 0 |
Reserved |
| USERINTMASKCLEAR | |
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LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect;
Table 34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
USERINTMASKCLEAR | MDIO user command complete interrupt mask clear for USERINTMASKED[1:0], | ||
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| respectively. Setting a bit to 1 will disable further user command complete interrupts |
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| for that particular USERACCESS register. USERINTMASKCLEAR[0] and |
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| USERINTMASKCLEAR[1] correspond to USERACCESS0 and USERACCESS1, |
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| respectively. Writing a 0 to this register has no effect. |
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| 0 | MDIO user command complete interrupts for the MDIO user access register n |
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| (USERACCESSn) are enabled. |
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| 1 | MDIO user command complete interrupts for the MDIO user access register n |
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| (USERACCESSn) are disabled. |
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | 79 | |
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