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Texas Instruments TMS320DM646x Receive Interrupt Mask Set Register RXINTMASKSET, Field, Value

Models: TMS320DM646x

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5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)

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Ethernet Media Access Controller (EMAC) Registers

5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)

The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 55 and described in Table 54.

	Figure 55. Receive Interrupt Mask Set Register (RXINTMASKSET)
31							16
			Reserved
				R-0
15							8
			Reserved
				R-0
7	6	5	4	3	2	1	0
RX7MASK	RX6MASK	RX5MASK	RX4MASK	RX3MASK	RX2MASK	RX1MASK	RX0MASK
R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0

LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n= value after reset

Table 54. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions

Bit	Field	Value	Description
31-8	Reserved	0	Reserved
7	RX7MASK	0-1	Receive channel 7 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
6	RX6MASK	0-1	Receive channel 6 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
5	RX5MASK	0-1	Receive channel 5 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
4	RX4MASK	0-1	Receive channel 4 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
3	RX3MASK	0-1	Receive channel 3 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
2	RX2MASK	0-1	Receive channel 2 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
1	RX1MASK	0-1	Receive channel 1 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
0	RX0MASK	0-1	Receive channel 0 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.

98	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	SPRUEQ6–December 2007
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Texas Instruments TMS320DM646x manual Receive Interrupt Mask Set Register RXINTMASKSET, Field, Value, Description

Contents

Management Data Input/Output MDIO Module TMS320DM646x DMSoC Ethernet Media Access Controller EMACUsers Guide SPRUEQ6-December Submit Documentation FeedbackContents PHY Acknowledge Status Register ALIVE MAC Hash Address Register 1 MACHASH1 List of Figures List of FiguresReceive Interrupt Mask Set Register RXINTMASKSET List of Tables MAC Status Register MACSTATUS Field Descriptions Soft Reset Register SOFTRESET Field DescriptionsMAC Control Register MACCONTROL Field Descriptions FIFO Control Register FIFOCONTROL Field DescriptionsAbout This Manual Read This FirstPreface Notational ConventionsRelated Documentation From Texas Instruments Read This First1 Introduction Users Guide1.2 Features 1.1 Purpose of the Peripheral1.3 Functional Block Diagram Figure 1. EMAC and MDIO Block Diagram2.1 Clock Control 1.4 Industry Standards Compliance Statement2 Architecture 2.1.1 MII Clocking2.2 Memory Map 2.3 Signal DescriptionsFigure 2. Ethernet Configuration-MII Connections 2.3.1 Media Independent Interface MII ConnectionsArchitecture Table 1. EMAC and MDIO Signals for MII InterfaceSignal Type2.3.2 Gigabit Media Independent Interface GMII Connections Figure 3. Ethernet Configuration-GMII ConnectionsTable 2. EMAC and MDIO Signals for GMII Interface MTCLK GMTCLK RFTCLK MTXD7−0 MTXEN MCOL MCRS MRCLK MRXD7−0 MRXDV MRXERArchitecture Table 2. EMAC and MDIO Signals for GMII Interface continuedSignal TypeFigure 4. Ethernet Frame Format 2.4 Ethernet Protocol Overview2.4.1 Ethernet Frame Format Table 3. Ethernet Frame Description2.5.1 Packet Buffer Descriptors 2.4.2 Ethernet’s Multiple Access Protocol2.5 Programming Interface Figure 5. Basic Descriptor FormatTable 4. Basic Descriptor Description Figure 6. Typical Descriptor Linked List2.5.2 Transmit and Receive Descriptor Queues 2.5.3 Transmit and Receive EMAC Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format 2.5.4 Transmit Buffer Descriptor FormatFigure 7. Transmit Buffer Descriptor Format Architecture2.5.4.3 Buffer Offset 2.5.4.1 Next Descriptor Pointer2.5.4.2 Buffer Pointer 2.5.4.4 Buffer Length2.5.4.9 End of Queue EOQ Flag 2.5.4.7 End of Packet EOP Flag2.5.4.8 Ownership OWNER Flag 2.5.4.10 Teardown Complete TDOWNCMPLT Flag2.5.5.2 Buffer Pointer 2.5.5 Receive Buffer Descriptor Format2.5.5.1 Next Descriptor Pointer Figure 8. Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format 2.5.5.3 Buffer Offset2.5.5.6 Start of Packet SOP Flag 2.5.5.4 Buffer Length2.5.5.5 Packet Length 2.5.5.7 End of Packet EOP Flag2.5.5.20 CRC Error CRCERROR Flag 2.5.5.18 Code Error CODEERROR Flag2.5.5.19 Alignment Error ALIGNERROR Flag 2.5.5.10 Teardown Complete TDOWNCMPLT Flag2.5.5.21 No Match NOMATCH Flag Figure 9. EMAC Control Module Block Diagram2.6 EMAC Control Module 2.6.1 Internal Memory2.6.3.1 Transmit Pulse Interrupt 2.6.3 Interrupt ControlTable 5. EMAC Control Module Interrupts 2.6.3.2 Receive Pulse Interrupt2.6.4 Interrupt Pacing 2.6.3.3 Receive Threshold Pulse Interrupt2.6.3.4 Miscellaneous Pulse Interrupt 2.7.1 MDIO Module Components Figure 10. MDIO Module Block Diagram2.7 MDIO Module 2.7.1.1 MDIO Clock Generator2.7.1.3 Active PHY Monitoring 2.7.1.4 PHY Register User Access2.7.1.2 Global PHY Detection and Link State Monitoring 2.7.2 MDIO Module Operational Overview2.7.2.3 Reading Data From a PHY Register 2.7.2.1 Initializing the MDIO Module2.7.2.2 Writing Data To a PHY Register 2.7.2.4 Example of MDIO Register Access Code Example 3. MDIO Register Access Macros2.8.1 EMAC Module Components Figure 11. EMAC Module Block Diagram2.8 EMAC Module 2.8.1.1 Receive DMA Engine2.8.1.4 Receive Address 2.8.1.12 Clock and Reset Logic2.8.1.3 MAC Receiver 2.8.1.5 Transmit DMA Engine2.8.2 EMAC Module Operational Overview 2.9.1.1 Receive Control 2.9 Media Independent Interface MII2.9.1 Data Reception 2.9.1.2 Receive Inter-Frame Interval2.9.1.3.1 Collision-Based Receive Buffer Flow Control 2.9.1.3.2 IEEE 802.3x-Based Receive Buffer Flow Control2.9.2.2 CRC Insertion 2.9.2 Data Transmission2.9.2.1 Transmit Control 2.9.2.3 Adaptive Performance Optimization APO2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support2.10.2 Receive Channel Enabling 2.10.1 Receive DMA Host Configuration2.10 Packet Receive Operation 2.10.5 Host Free Buffer Tracking 2.10.3 Receive Address Matching2.10.4 Hardware Receive QOS Support 2.10.6 Receive Channel Teardown 2.10.7 Receive Frame ClassificationRXCAFEN 2.10.8 Promiscuous Receive ModeTable 6. Receive Frame Treatment Summary RXCEFENTable 7. Middle of Frame Overrun Treatment Table 6. Receive Frame Treatment Summary continued2.10.9 Receive Overrun 2.12 Receive and Transmit Latency 2.11.1 Transmit DMA Host Configuration2.11 Packet Transmit Operation 2.11.2 Transmit Channel Teardown2.13 Transfer Node Priority 2.14 Reset Considerations2.14.1 Software Reset Considerations 2.15.1 Enabling the EMAC/MDIO Peripheral 2.14.2 Hardware Reset Considerations2.15 Initialization 2.15.2 EMAC Control Module InitializationSubmit Documentation Feedback Example 4. EMAC Control Module Initialization CodeArchitecture 2.15.3 MDIO Module Initialization Example 5. MDIO Module Initialization Code2.15.4 EMAC Module Initialization 2.16.1 EMAC Module Interrupt Events and Requests Figure 12. EMAC Control Module Interrupt Logic Diagram2.16 Interrupt Support 2.16.1.1 Receive Threshold Interrupts2.16.1.2 Transmit Packet Completion Interrupts 2.16.1.3 Receive Packet Completion Interrupts2.16.1.5 Host Error Interrupt 2.16.1.4 Statistics Interrupt2.16.2.1 Link Change Interrupt 2.16.2.2 User Access Completion Interrupt2.16.2 MDIO Module Interrupt Events and Requests 2.16.3 Proper Interrupt ProcessingTable 8. Emulation Control 2.17 Power Management2.18 Emulation Considerations Table 9. EMAC Control Module Registers 3 EMAC Control Module Registers3.1 EMAC Control Module Identification and Version Register CMIDVER Field Descriptions3.3 EMAC Control Module Emulation Control Register CMEMCONTROL 3.2 EMAC Control Module Software Reset Register CMSOFTRESETFigure 14. EMAC Control Module Software Reset Register CMSOFTRESET Figure 15. EMAC Control Module Emulation Control Register CMEMCONTROLTable 13. EMAC Control Module Interrupt Control Register CMINTCTRL 3.4 EMAC Control Module Interrupt Control Register CMINTCTRLFigure 16. EMAC Control Module Interrupt Control Register CMINTCTRL Field DescriptionsCMRXTHRESHINTEN 3.5 EMAC Control Module Receive Threshold Interrupt Enable Register3.6 EMAC Control Module Receive Interrupt Enable Register CMRXINTEN CMRXTHRESHINTEN3.7 EMAC Control Module Transmit Interrupt Enable Register CMTXINTEN Field DescriptionsField Descriptions CMRXTHRESHINTSTAT 3.9 EMAC Control Module Receive Threshold Interrupt Status RegisterCMRXTHRESHINTSTAT CMRXTHRESHINTSTAT Field DescriptionsField Descriptions Field Descriptions 3.13 EMAC Control Module Receive Interrupts per Millisecond Register CMRXINTMAX Table 24. Management Data Input/Output MDIO Registers 4 MDIO Registers4.1 MDIO Version Register VERSION Figure 27. MDIO Version Register VERSIONTable 26. MDIO Control Register CONTROL Field Descriptions 4.2 MDIO Control Register CONTROLFigure 28. MDIO Control Register CONTROL MDIO RegistersFigure 29. PHY Acknowledge Status Register ALIVE 4.3 PHY Acknowledge Status Register ALIVE4.4 PHY Link Status Register LINK Table 27. PHY Acknowledge Status Register ALIVE Field Descriptions4.5 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW Field Descriptions4.6 MDIO Link Status Change Interrupt Masked Register LINKINTMASKED Field Descriptions4.7 MDIO User Command Complete Interrupt Unmasked Register USERINTRAW Field DescriptionsField Descriptions Field Descriptions USERINTMASKCLEAR Figure 36. MDIO User Command Complete Interrupt Mask Clear RegisterFigure 36 and described in Table Field DescriptionsTable 35. MDIO User Access Register 0 USERACCESS0 Field Descriptions 4.11 MDIO User Access Register 0 USERACCESS0Figure 37. MDIO User Access Register 0 USERACCESS0 MDIO RegistersMDIO Registers 4.12 MDIO User PHY Select Register 0 USERPHYSEL0Figure 38. MDIO User PHY Select Register 0 USERPHYSEL0 FieldTable 37. MDIO User Access Register 1 USERACCESS1 Field Descriptions 4.13 MDIO User Access Register 1 USERACCESS1Figure 39. MDIO User Access Register 1 USERACCESS1 MDIO RegistersMDIO Registers 4.14 MDIO User PHY Select Register 1 USERPHYSEL1Figure 40. MDIO User PHY Select Register 1 USERPHYSEL1 FieldEthernet Media Access Controller EMAC Registers 5 Ethernet Media Access Controller EMAC RegistersTable 39. Ethernet Media Access Controller EMAC Registers AcronymOffset Table 39. Ethernet Media Access Controller EMAC Registers continuedEthernet Media Access Controller EMAC Registers AcronymOffset Table 39. Ethernet Media Access Controller EMAC Registers continuedEthernet Media Access Controller EMAC Registers AcronymFigure 41. Transmit Identification and Version Register TXIDVER 5.1 Transmit Identification and Version Register TXIDVER5.2 Transmit Control Register TXCONTROL Figure 42. Transmit Control Register TXCONTROLFigure 43. Transmit Teardown Register TXTEARDOWN Ethernet Media Access Controller EMAC Registers5.3 Transmit Teardown Register TXTEARDOWN Table 42. Transmit Teardown Register TXTEARDOWN Field DescriptionsFigure 44. Receive Identification and Version Register RXIDVER 5.4 Receive Identification and Version Register RXIDVER5.5 Receive Control Register RXCONTROL Figure 45. Receive Control Register RXCONTROLFigure 46. Receive Teardown Register RXTEARDOWN Ethernet Media Access Controller EMAC Registers5.6 Receive Teardown Register RXTEARDOWN Table 45. Receive Teardown Register RXTEARDOWN Field DescriptionsFigure 47. Transmit Interrupt Status Unmasked Register TXINTSTATRAW Ethernet Media Access Controller EMAC Registers5.7 Transmit Interrupt Status Unmasked Register TXINTSTATRAW FieldFigure 48. Transmit Interrupt Status Masked Register TXINTSTATMASKED Ethernet Media Access Controller EMAC Registers5.8 Transmit Interrupt Status Masked Register TXINTSTATMASKED FieldFigure 49. Transmit Interrupt Mask Set Register TXINTMASKSET Ethernet Media Access Controller EMAC Registers5.9 Transmit Interrupt Mask Set Register TXINTMASKSET FieldFigure 50. Transmit Interrupt Mask Clear Register TXINTMASKCLEAR Ethernet Media Access Controller EMAC Registers5.10 Transmit Interrupt Mask Clear Register TXINTMASKCLEAR FieldFigure 51. MAC Input Vector Register MACINVECTOR 5.11 MAC Input Vector Register MACINVECTOR5.12 MAC End Of Interrupt Vector Register MACEOIVECTOR Table 50. MAC Input Vector Register MACINVECTOR Field DescriptionsFigure 53. Receive Interrupt Status Unmasked Register RXINTSTATRAW Ethernet Media Access Controller EMAC Registers5.13 Receive Interrupt Status Unmasked Register RXINTSTATRAW FieldFigure 54. Receive Interrupt Status Masked Register RXINTSTATMASKED Ethernet Media Access Controller EMAC Registers5.14 Receive Interrupt Status Masked Register RXINTSTATMASKED FieldFigure 55. Receive Interrupt Mask Set Register RXINTMASKSET Ethernet Media Access Controller EMAC Registers5.15 Receive Interrupt Mask Set Register RXINTMASKSET FieldFigure 56. Receive Interrupt Mask Clear Register RXINTMASKCLEAR Ethernet Media Access Controller EMAC Registers5.16 Receive Interrupt Mask Clear Register RXINTMASKCLEAR FieldFigure 57. MAC Interrupt Status Unmasked Register MACINTSTATRAW 5.17 MAC Interrupt Status Unmasked Register MACINTSTATRAW5.18 MAC Interrupt Status Masked Register MACINTSTATMASKED Figure 58. MAC Interrupt Status Masked Register MACINTSTATMASKEDFigure 59. MAC Interrupt Mask Set Register MACINTMASKSET 5.19 MAC Interrupt Mask Set Register MACINTMASKSET5.20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR Figure 60. MAC Interrupt Mask Clear Register MACINTMASKCLEARField Descriptions Field Ethernet Media Access Controller EMAC RegistersField Descriptions continued ValueField Ethernet Media Access Controller EMAC RegistersField Descriptions continued ValueEthernet Media Access Controller EMAC Registers 5.22 Receive Unicast Enable Set Register RXUNICASTSETFigure 62. Receive Unicast Enable Set Register RXUNICASTSET FieldFigure 63. Receive Unicast Clear Register RXUNICASTCLEAR Ethernet Media Access Controller EMAC Registers5.23 Receive Unicast Clear Register RXUNICASTCLEAR FieldFigure 64. Receive Maximum Length Register RXMAXLEN 5.24 Receive Maximum Length Register RXMAXLEN5.25 Receive Buffer Offset Register RXBUFFEROFFSET Table 63. Receive Maximum Length Register RXMAXLEN Field DescriptionsField Descriptions Field Descriptions5.28 Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER described in TableFigure 69. MAC Control Register MACCONTROL Ethernet Media Access Controller EMAC Registers5.29 MAC Control Register MACCONTROL Table 68. MAC Control Register MACCONTROL Field DescriptionsSubmit Documentation Feedback FieldDescription ValueFigure 70. MAC Status Register MACSTATUS Ethernet Media Access Controller EMAC Registers5.30 MAC Status Register MACSTATUS Table 69. MAC Status Register MACSTATUS Field DescriptionsValue Table 69. MAC Status Register MACSTATUS Field Descriptions continuedField DescriptionFigure 71. Emulation Control Register EMCONTROL 5.31 Emulation Control Register EMCONTROL5.32 FIFO Control Register FIFOCONTROL Table 70. Emulation Control Register EMCONTROL Field DescriptionsFigure 73. MAC Configuration Register MACCONFIG 5.33 MAC Configuration Register MACCONFIG5.34 Soft Reset Register SOFTRESET Table 72. MAC Configuration Register MACCONFIG Field DescriptionsFigure 75. MAC Source Address Low Bytes Register MACSRCADDRLO 5.35 MAC Source Address Low Bytes Register MACSRCADDRLO5.36 MAC Source Address High Bytes Register MACSRCADDRHI Figure 76. MAC Source Address High Bytes Register MACSRCADDRHIFigure 77. MAC Hash Address Register 1 MACHASH1 5.37 MAC Hash Address Register 1 MACHASH15.38 MAC Hash Address Register 2 MACHASH2 Table 76. MAC Hash Address Register 1 MACHASH1 Field DescriptionsFigure 79. Back Off Random Number Generator Test Register BOFFTEST 5.39 Back Off Test Register BOFFTEST5.40 Transmit Pacing Algorithm Test Register TPACETEST Table 78. Back Off Test Register BOFFTEST Field DescriptionsFigure 81. Receive Pause Timer Register RXPAUSE 5.41 Receive Pause Timer Register RXPAUSE5.42 Transmit Pause Timer Register TXPAUSE Table 80. Receive Pause Timer Register RXPAUSE Field DescriptionsFigure 83. MAC Address Low Bytes Register MACADDRLO Ethernet Media Access Controller EMAC Registers5.43 MAC Address Low Bytes Register MACADDRLO Table 82. MAC Address Low Bytes Register MACADDRLO Field DescriptionsFigure 84. MAC Address High Bytes Register MACADDRHI 5.44 MAC Address High Bytes Register MACADDRHI5.45 MAC Index Register MACINDEX Figure 85. MAC Index Register MACINDEXField Descriptions 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register TXnHDP5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register RXnHDP Field DescriptionsFigure 88. Transmit Channel n Completion Pointer Register TX nCP 5.48 Transmit Channel 0-7 Completion Pointer Register TXnCP5.49 Receive Channel 0-7 Completion Pointer Register RXnCP Figure 89. Receive Channel n Completion Pointer Register RX nCP5.50.1 Good Receive Frames Register RXGOODFRAMES 5.50 Network Statistics RegistersFigure 90. Statistics Register 5.50.2 Broadcast Receive Frames Register RXBCASTFRAMES5.50.4 Pause Receive Frames Register RXPAUSEFRAMES 5.50.5 Receive CRC Errors Register RXCRCERRORS5.50.6 Receive Alignment/Code Errors Register RXALIGNCODEERRORS 5.50.7 Receive Oversized Frames Register RXOVERSIZED5.50.10 Receive Frame Fragments Register RXFRAGMENTS 5.50.8 Receive Jabber Frames Register RXJABBER5.50.9 Receive Undersized Frames Register RXUNDERSIZED 5.50.11 Filtered Receive Frames Register RXFILTERED5.50.14 Good Transmit Frames Register TXGOODFRAMES 5.50.12 Receive QOS Filtered Frames Register RXQOSFILTERED5.50.13 Receive Octet Frames Register RXOCTETS 5.50.15 Broadcast Transmit Frames Register TXBCASTFRAMES5.50.18 Deferred Transmit Frames Register TXDEFERRED 5.50.16 Multicast Transmit Frames Register TXMCASTFRAMES5.50.17 Pause Transmit Frames Register TXPAUSEFRAMES 5.50.19 Transmit Collision Frames Register TXCOLLISION5.50.21 Transmit Multiple Collision Frames Register TXMULTICOLL 5.50.24 Transmit Underrun Error Register TXUNDERRUN5.50.25 Transmit Carrier Sense Errors Register TXCARRIERSENSE 5.50.22 Transmit Excessive Collision Frames Register TXEXCESSIVECOLL5.50.26 Transmit Octet Frames Register TXOCTETS 5.50.27 Transmit and Receive 64 Octet Frames Register FRAME645.50.33 Network Octet Frames Register NETOCTETS Ethernet Media Access Controller EMAC Registers 5.50.36 Receive DMA Overruns Register RXDMAOVERRUNSAppendix A Glossary Appendix ATable A-1. Physical Layer Definitions Products power.ti.comIMPORTANT NOTICE Applications