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Texas Instruments TMS320DM646x manual MAC Status Register MACSTATUS, Field, Description

Models: TMS320DM646x

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5.30 MAC Status Register (MACSTATUS)

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Ethernet Media Access Controller (EMAC) Registers

5.30 MAC Status Register (MACSTATUS)

The MAC status register (MACSTATUS) is shown in Figure 70 and described in Table 69.

Figure 70. MAC Status Register (MACSTATUS)

31	30	24	23	20	19	18	16
IDLE		Reserved		TXERRCODE	Rsvd		TXERRCH
R-0		R-0		R-0	R-0		R-0
	15	12	11	10			8
		RXERRCODE	Reserved		RXERRCH
		R-0	R-0			R-0
	7		3	2		1	0
		Reserved		RXQOSACT	RXFLOWACT		TXFLOWACT
		R-0		R-0		R-0	R-0
LEGEND: R = Read only; R/W = Read/Write; -n= value after reset

Table 69. MAC Status Register (MACSTATUS) Field Descriptions

Bit	Field	Value	Description
31	IDLE		EMAC idle bit. This bit is set to 0 at reset; one clock after reset it goes to 1.
		0	The EMAC is not idle.
		1	The EMAC is in the idle state.
30-24	Reserved	0	Reserved
23-20	TXERRCODE	0-Fh	Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors.
			The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host
			error interrupts require hardware reset in order to recover. A 0 packet length is an error, but it is not
			detected.
		0	No error
		1h	SOP error; the buffer is the first buffer in a packet, but the SOP bit is not set in software.
		2h	Ownership bit not set in SOP buffer
		3h	Zero next buffer descriptor pointer without EOP
		4h	Zero buffer pointer
		5h	Zero buffer length
		6h	Packet length error (sum of buffers is less than packet length)
19	Reserved	0	Reserved
18-16	TXERRCH	0-7h	Transmit host error channel. These bits indicate which transmit channel the host error occurred on.
			This field is cleared to 0 on a host read.
		0	The host error occurred on transmit channel 0
		1h	The host error occurred on transmit channel 1
		2h	The host error occurred on transmit channel 2
		3h	The host error occurred on transmit channel 3
		4h	The host error occurred on transmit channel 4
		5h	The host error occurred on transmit channel 5
		6h	The host error occurred on transmit channel 6
		7h	The host error occurred on transmit channel 7
15-12	RXERRCODE	0-Fh	Receive host error code. These bits indicate that EMAC detected receive DMA related host errors.
			The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host
			error interrupts require hardware reset in order to recover.
		0	No error
		2h	Ownership bit not set in SOP buffer
		4h	Zero buffer pointer
11	Reserved	0	Reserved
112	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)			SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x manual MAC Status Register MACSTATUS Field Descriptions, Submit Documentation Feedback

Contents

Users Guide TMS320DM646x DMSoC Ethernet Media Access Controller EMACManagement Data Input/Output MDIO Module SPRUEQ6-December Submit Documentation FeedbackContents PHY Acknowledge Status Register ALIVE MAC Hash Address Register 1 MACHASH1 List of Figures List of FiguresReceive Interrupt Mask Set Register RXINTMASKSET List of Tables Soft Reset Register SOFTRESET Field Descriptions MAC Control Register MACCONTROL Field DescriptionsMAC Status Register MACSTATUS Field Descriptions FIFO Control Register FIFOCONTROL Field DescriptionsRead This First PrefaceAbout This Manual Notational ConventionsRelated Documentation From Texas Instruments Read This FirstUsers Guide 1.2 Features1 Introduction 1.1 Purpose of the Peripheral1.3 Functional Block Diagram Figure 1. EMAC and MDIO Block Diagram1.4 Industry Standards Compliance Statement 2 Architecture2.1 Clock Control 2.1.1 MII Clocking2.3 Signal Descriptions Figure 2. Ethernet Configuration-MII Connections2.2 Memory Map 2.3.1 Media Independent Interface MII ConnectionsTable 1. EMAC and MDIO Signals for MII Interface SignalArchitecture TypeFigure 3. Ethernet Configuration-GMII Connections Table 2. EMAC and MDIO Signals for GMII Interface2.3.2 Gigabit Media Independent Interface GMII Connections MTCLK GMTCLK RFTCLK MTXD7−0 MTXEN MCOL MCRS MRCLK MRXD7−0 MRXDV MRXERTable 2. EMAC and MDIO Signals for GMII Interface continued SignalArchitecture Type2.4 Ethernet Protocol Overview 2.4.1 Ethernet Frame FormatFigure 4. Ethernet Frame Format Table 3. Ethernet Frame Description2.4.2 Ethernet’s Multiple Access Protocol 2.5 Programming Interface2.5.1 Packet Buffer Descriptors Figure 5. Basic Descriptor FormatTable 4. Basic Descriptor Description Figure 6. Typical Descriptor Linked List2.5.2 Transmit and Receive Descriptor Queues 2.5.3 Transmit and Receive EMAC Interrupts 2.5.4 Transmit Buffer Descriptor Format Figure 7. Transmit Buffer Descriptor FormatExample 1. Transmit Buffer Descriptor in C Structure Format Architecture2.5.4.1 Next Descriptor Pointer 2.5.4.2 Buffer Pointer2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length2.5.4.7 End of Packet EOP Flag 2.5.4.8 Ownership OWNER Flag2.5.4.9 End of Queue EOQ Flag 2.5.4.10 Teardown Complete TDOWNCMPLT Flag2.5.5 Receive Buffer Descriptor Format 2.5.5.1 Next Descriptor Pointer2.5.5.2 Buffer Pointer Figure 8. Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format 2.5.5.3 Buffer Offset2.5.5.4 Buffer Length 2.5.5.5 Packet Length2.5.5.6 Start of Packet SOP Flag 2.5.5.7 End of Packet EOP Flag2.5.5.18 Code Error CODEERROR Flag 2.5.5.19 Alignment Error ALIGNERROR Flag2.5.5.20 CRC Error CRCERROR Flag 2.5.5.10 Teardown Complete TDOWNCMPLT FlagFigure 9. EMAC Control Module Block Diagram 2.6 EMAC Control Module2.5.5.21 No Match NOMATCH Flag 2.6.1 Internal Memory2.6.3 Interrupt Control Table 5. EMAC Control Module Interrupts2.6.3.1 Transmit Pulse Interrupt 2.6.3.2 Receive Pulse Interrupt2.6.3.4 Miscellaneous Pulse Interrupt 2.6.3.3 Receive Threshold Pulse Interrupt2.6.4 Interrupt Pacing Figure 10. MDIO Module Block Diagram 2.7 MDIO Module2.7.1 MDIO Module Components 2.7.1.1 MDIO Clock Generator2.7.1.4 PHY Register User Access 2.7.1.2 Global PHY Detection and Link State Monitoring2.7.1.3 Active PHY Monitoring 2.7.2 MDIO Module Operational Overview2.7.2.2 Writing Data To a PHY Register 2.7.2.1 Initializing the MDIO Module2.7.2.3 Reading Data From a PHY Register 2.7.2.4 Example of MDIO Register Access Code Example 3. MDIO Register Access MacrosFigure 11. EMAC Module Block Diagram 2.8 EMAC Module2.8.1 EMAC Module Components 2.8.1.1 Receive DMA Engine2.8.1.12 Clock and Reset Logic 2.8.1.3 MAC Receiver2.8.1.4 Receive Address 2.8.1.5 Transmit DMA Engine2.8.2 EMAC Module Operational Overview 2.9 Media Independent Interface MII 2.9.1 Data Reception2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval2.9.1.3.1 Collision-Based Receive Buffer Flow Control 2.9.1.3.2 IEEE 802.3x-Based Receive Buffer Flow Control2.9.2 Data Transmission 2.9.2.1 Transmit Control2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization APO2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration2.10.2 Receive Channel Enabling 2.10.4 Hardware Receive QOS Support 2.10.3 Receive Address Matching2.10.5 Host Free Buffer Tracking 2.10.6 Receive Channel Teardown 2.10.7 Receive Frame Classification2.10.8 Promiscuous Receive Mode Table 6. Receive Frame Treatment SummaryRXCAFEN RXCEFEN2.10.9 Receive Overrun Table 6. Receive Frame Treatment Summary continuedTable 7. Middle of Frame Overrun Treatment 2.11.1 Transmit DMA Host Configuration 2.11 Packet Transmit Operation2.12 Receive and Transmit Latency 2.11.2 Transmit Channel Teardown2.14.1 Software Reset Considerations 2.14 Reset Considerations2.13 Transfer Node Priority 2.14.2 Hardware Reset Considerations 2.15 Initialization2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.2 EMAC Control Module InitializationArchitecture Example 4. EMAC Control Module Initialization CodeSubmit Documentation Feedback 2.15.3 MDIO Module Initialization Example 5. MDIO Module Initialization Code2.15.4 EMAC Module Initialization Figure 12. EMAC Control Module Interrupt Logic Diagram 2.16 Interrupt Support2.16.1 EMAC Module Interrupt Events and Requests 2.16.1.1 Receive Threshold Interrupts2.16.1.2 Transmit Packet Completion Interrupts 2.16.1.3 Receive Packet Completion Interrupts2.16.1.5 Host Error Interrupt 2.16.1.4 Statistics Interrupt2.16.2.2 User Access Completion Interrupt 2.16.2 MDIO Module Interrupt Events and Requests2.16.2.1 Link Change Interrupt 2.16.3 Proper Interrupt Processing2.18 Emulation Considerations 2.17 Power ManagementTable 8. Emulation Control 3 EMAC Control Module Registers 3.1 EMAC Control Module Identification and Version Register CMIDVERTable 9. EMAC Control Module Registers Field Descriptions3.2 EMAC Control Module Software Reset Register CMSOFTRESET Figure 14. EMAC Control Module Software Reset Register CMSOFTRESET3.3 EMAC Control Module Emulation Control Register CMEMCONTROL Figure 15. EMAC Control Module Emulation Control Register CMEMCONTROL3.4 EMAC Control Module Interrupt Control Register CMINTCTRL Figure 16. EMAC Control Module Interrupt Control Register CMINTCTRLTable 13. EMAC Control Module Interrupt Control Register CMINTCTRL Field Descriptions3.5 EMAC Control Module Receive Threshold Interrupt Enable Register 3.6 EMAC Control Module Receive Interrupt Enable Register CMRXINTENCMRXTHRESHINTEN CMRXTHRESHINTEN3.7 EMAC Control Module Transmit Interrupt Enable Register CMTXINTEN Field DescriptionsField Descriptions 3.9 EMAC Control Module Receive Threshold Interrupt Status Register CMRXTHRESHINTSTATCMRXTHRESHINTSTAT CMRXTHRESHINTSTAT Field DescriptionsField Descriptions Field Descriptions 3.13 EMAC Control Module Receive Interrupts per Millisecond Register CMRXINTMAX 4 MDIO Registers 4.1 MDIO Version Register VERSIONTable 24. Management Data Input/Output MDIO Registers Figure 27. MDIO Version Register VERSION4.2 MDIO Control Register CONTROL Figure 28. MDIO Control Register CONTROLTable 26. MDIO Control Register CONTROL Field Descriptions MDIO Registers4.3 PHY Acknowledge Status Register ALIVE 4.4 PHY Link Status Register LINKFigure 29. PHY Acknowledge Status Register ALIVE Table 27. PHY Acknowledge Status Register ALIVE Field Descriptions4.5 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW Field Descriptions4.6 MDIO Link Status Change Interrupt Masked Register LINKINTMASKED Field Descriptions4.7 MDIO User Command Complete Interrupt Unmasked Register USERINTRAW Field DescriptionsField Descriptions Field Descriptions Figure 36. MDIO User Command Complete Interrupt Mask Clear Register Figure 36 and described in TableUSERINTMASKCLEAR Field Descriptions4.11 MDIO User Access Register 0 USERACCESS0 Figure 37. MDIO User Access Register 0 USERACCESS0Table 35. MDIO User Access Register 0 USERACCESS0 Field Descriptions MDIO Registers4.12 MDIO User PHY Select Register 0 USERPHYSEL0 Figure 38. MDIO User PHY Select Register 0 USERPHYSEL0MDIO Registers Field4.13 MDIO User Access Register 1 USERACCESS1 Figure 39. MDIO User Access Register 1 USERACCESS1Table 37. MDIO User Access Register 1 USERACCESS1 Field Descriptions MDIO Registers4.14 MDIO User PHY Select Register 1 USERPHYSEL1 Figure 40. MDIO User PHY Select Register 1 USERPHYSEL1MDIO Registers Field5 Ethernet Media Access Controller EMAC Registers Table 39. Ethernet Media Access Controller EMAC RegistersEthernet Media Access Controller EMAC Registers AcronymTable 39. Ethernet Media Access Controller EMAC Registers continued Ethernet Media Access Controller EMAC RegistersOffset AcronymTable 39. Ethernet Media Access Controller EMAC Registers continued Ethernet Media Access Controller EMAC RegistersOffset Acronym5.1 Transmit Identification and Version Register TXIDVER 5.2 Transmit Control Register TXCONTROLFigure 41. Transmit Identification and Version Register TXIDVER Figure 42. Transmit Control Register TXCONTROLEthernet Media Access Controller EMAC Registers 5.3 Transmit Teardown Register TXTEARDOWNFigure 43. Transmit Teardown Register TXTEARDOWN Table 42. Transmit Teardown Register TXTEARDOWN Field Descriptions5.4 Receive Identification and Version Register RXIDVER 5.5 Receive Control Register RXCONTROLFigure 44. Receive Identification and Version Register RXIDVER Figure 45. Receive Control Register RXCONTROLEthernet Media Access Controller EMAC Registers 5.6 Receive Teardown Register RXTEARDOWNFigure 46. Receive Teardown Register RXTEARDOWN Table 45. Receive Teardown Register RXTEARDOWN Field DescriptionsEthernet Media Access Controller EMAC Registers 5.7 Transmit Interrupt Status Unmasked Register TXINTSTATRAWFigure 47. Transmit Interrupt Status Unmasked Register TXINTSTATRAW FieldEthernet Media Access Controller EMAC Registers 5.8 Transmit Interrupt Status Masked Register TXINTSTATMASKEDFigure 48. Transmit Interrupt Status Masked Register TXINTSTATMASKED FieldEthernet Media Access Controller EMAC Registers 5.9 Transmit Interrupt Mask Set Register TXINTMASKSETFigure 49. Transmit Interrupt Mask Set Register TXINTMASKSET FieldEthernet Media Access Controller EMAC Registers 5.10 Transmit Interrupt Mask Clear Register TXINTMASKCLEARFigure 50. Transmit Interrupt Mask Clear Register TXINTMASKCLEAR Field5.11 MAC Input Vector Register MACINVECTOR 5.12 MAC End Of Interrupt Vector Register MACEOIVECTORFigure 51. MAC Input Vector Register MACINVECTOR Table 50. MAC Input Vector Register MACINVECTOR Field DescriptionsEthernet Media Access Controller EMAC Registers 5.13 Receive Interrupt Status Unmasked Register RXINTSTATRAWFigure 53. Receive Interrupt Status Unmasked Register RXINTSTATRAW FieldEthernet Media Access Controller EMAC Registers 5.14 Receive Interrupt Status Masked Register RXINTSTATMASKEDFigure 54. Receive Interrupt Status Masked Register RXINTSTATMASKED FieldEthernet Media Access Controller EMAC Registers 5.15 Receive Interrupt Mask Set Register RXINTMASKSETFigure 55. Receive Interrupt Mask Set Register RXINTMASKSET FieldEthernet Media Access Controller EMAC Registers 5.16 Receive Interrupt Mask Clear Register RXINTMASKCLEARFigure 56. Receive Interrupt Mask Clear Register RXINTMASKCLEAR Field5.17 MAC Interrupt Status Unmasked Register MACINTSTATRAW 5.18 MAC Interrupt Status Masked Register MACINTSTATMASKEDFigure 57. MAC Interrupt Status Unmasked Register MACINTSTATRAW Figure 58. MAC Interrupt Status Masked Register MACINTSTATMASKED5.19 MAC Interrupt Mask Set Register MACINTMASKSET 5.20 MAC Interrupt Mask Clear Register MACINTMASKCLEARFigure 59. MAC Interrupt Mask Set Register MACINTMASKSET Figure 60. MAC Interrupt Mask Clear Register MACINTMASKCLEARField Descriptions Ethernet Media Access Controller EMAC Registers Field Descriptions continuedField ValueEthernet Media Access Controller EMAC Registers Field Descriptions continuedField Value5.22 Receive Unicast Enable Set Register RXUNICASTSET Figure 62. Receive Unicast Enable Set Register RXUNICASTSETEthernet Media Access Controller EMAC Registers FieldEthernet Media Access Controller EMAC Registers 5.23 Receive Unicast Clear Register RXUNICASTCLEARFigure 63. Receive Unicast Clear Register RXUNICASTCLEAR Field5.24 Receive Maximum Length Register RXMAXLEN 5.25 Receive Buffer Offset Register RXBUFFEROFFSETFigure 64. Receive Maximum Length Register RXMAXLEN Table 63. Receive Maximum Length Register RXMAXLEN Field DescriptionsField Descriptions Field Descriptions5.28 Receive Channel 0-7 Free Buffer Count Register RXnFREEBUFFER described in TableEthernet Media Access Controller EMAC Registers 5.29 MAC Control Register MACCONTROLFigure 69. MAC Control Register MACCONTROL Table 68. MAC Control Register MACCONTROL Field DescriptionsField DescriptionSubmit Documentation Feedback ValueEthernet Media Access Controller EMAC Registers 5.30 MAC Status Register MACSTATUSFigure 70. MAC Status Register MACSTATUS Table 69. MAC Status Register MACSTATUS Field DescriptionsTable 69. MAC Status Register MACSTATUS Field Descriptions continued FieldValue Description5.31 Emulation Control Register EMCONTROL 5.32 FIFO Control Register FIFOCONTROLFigure 71. Emulation Control Register EMCONTROL Table 70. Emulation Control Register EMCONTROL Field Descriptions5.33 MAC Configuration Register MACCONFIG 5.34 Soft Reset Register SOFTRESETFigure 73. MAC Configuration Register MACCONFIG Table 72. MAC Configuration Register MACCONFIG Field Descriptions5.35 MAC Source Address Low Bytes Register MACSRCADDRLO 5.36 MAC Source Address High Bytes Register MACSRCADDRHIFigure 75. MAC Source Address Low Bytes Register MACSRCADDRLO Figure 76. MAC Source Address High Bytes Register MACSRCADDRHI5.37 MAC Hash Address Register 1 MACHASH1 5.38 MAC Hash Address Register 2 MACHASH2Figure 77. MAC Hash Address Register 1 MACHASH1 Table 76. MAC Hash Address Register 1 MACHASH1 Field Descriptions5.39 Back Off Test Register BOFFTEST 5.40 Transmit Pacing Algorithm Test Register TPACETESTFigure 79. Back Off Random Number Generator Test Register BOFFTEST Table 78. Back Off Test Register BOFFTEST Field Descriptions5.41 Receive Pause Timer Register RXPAUSE 5.42 Transmit Pause Timer Register TXPAUSEFigure 81. Receive Pause Timer Register RXPAUSE Table 80. Receive Pause Timer Register RXPAUSE Field DescriptionsEthernet Media Access Controller EMAC Registers 5.43 MAC Address Low Bytes Register MACADDRLOFigure 83. MAC Address Low Bytes Register MACADDRLO Table 82. MAC Address Low Bytes Register MACADDRLO Field Descriptions5.44 MAC Address High Bytes Register MACADDRHI 5.45 MAC Index Register MACINDEXFigure 84. MAC Address High Bytes Register MACADDRHI Figure 85. MAC Index Register MACINDEX5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register TXnHDP 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register RXnHDPField Descriptions Field Descriptions5.48 Transmit Channel 0-7 Completion Pointer Register TXnCP 5.49 Receive Channel 0-7 Completion Pointer Register RXnCPFigure 88. Transmit Channel n Completion Pointer Register TX nCP Figure 89. Receive Channel n Completion Pointer Register RX nCP5.50 Network Statistics Registers Figure 90. Statistics Register5.50.1 Good Receive Frames Register RXGOODFRAMES 5.50.2 Broadcast Receive Frames Register RXBCASTFRAMES5.50.5 Receive CRC Errors Register RXCRCERRORS 5.50.6 Receive Alignment/Code Errors Register RXALIGNCODEERRORS5.50.4 Pause Receive Frames Register RXPAUSEFRAMES 5.50.7 Receive Oversized Frames Register RXOVERSIZED5.50.8 Receive Jabber Frames Register RXJABBER 5.50.9 Receive Undersized Frames Register RXUNDERSIZED5.50.10 Receive Frame Fragments Register RXFRAGMENTS 5.50.11 Filtered Receive Frames Register RXFILTERED5.50.12 Receive QOS Filtered Frames Register RXQOSFILTERED 5.50.13 Receive Octet Frames Register RXOCTETS5.50.14 Good Transmit Frames Register TXGOODFRAMES 5.50.15 Broadcast Transmit Frames Register TXBCASTFRAMES5.50.16 Multicast Transmit Frames Register TXMCASTFRAMES 5.50.17 Pause Transmit Frames Register TXPAUSEFRAMES5.50.18 Deferred Transmit Frames Register TXDEFERRED 5.50.19 Transmit Collision Frames Register TXCOLLISION5.50.24 Transmit Underrun Error Register TXUNDERRUN 5.50.25 Transmit Carrier Sense Errors Register TXCARRIERSENSE5.50.21 Transmit Multiple Collision Frames Register TXMULTICOLL 5.50.22 Transmit Excessive Collision Frames Register TXEXCESSIVECOLL5.50.26 Transmit Octet Frames Register TXOCTETS 5.50.27 Transmit and Receive 64 Octet Frames Register FRAME645.50.33 Network Octet Frames Register NETOCTETS Ethernet Media Access Controller EMAC Registers 5.50.36 Receive DMA Overruns Register RXDMAOVERRUNSAppendix A Glossary Appendix ATable A-1. Physical Layer Definitions power.ti.com IMPORTANT NOTICEProducts Applications