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Architecture

2.5.5Receive Buffer Descriptor Format

A receive (RX) buffer descriptor (Figure 8) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C structure.

2.5.5.1Next Descriptor Pointer

This pointer points to the 32–bit word aligned memory address of the next buffer descriptor in the receive queue. This pointer is used to create a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue. The software application must set this value prior to adding the descriptor to the active receive list. This pointer is not altered by the EMAC.

The value of pNext should never be altered once the descriptor is in an active receive queue, unless its current value is NULL. If the pNext pointer is initially NULL, and more empty buffers can be added to the pool, the software application may alter this pointer to point to a newly appended descriptor. The EMAC will use the new pointer value and proceed to the next descriptor unless the pNext value has already been read. In this latter case, the receiver will halt the receive channel in question, and the software application may restart it at that time. The software can detect this case by checking for an end of queue (EOQ) condition flag on the updated packet descriptor when it is returned by the EMAC.

2.5.5.2Buffer Pointer

The buffer pointer is the byte-aligned memory address of the memory buffer associated with the buffer descriptor. The software application must set this value prior to adding the descriptor to the active receive list. This pointer is not altered by the EMAC.

 

 

Figure 8. Receive Buffer Descriptor Format

 

 

Word 0

 

 

 

 

 

 

 

31

 

 

 

 

 

 

0

 

 

 

Next Descriptor Pointer

 

 

 

Word 1

 

 

 

 

 

 

 

31

 

 

 

 

 

 

0

 

 

 

Buffer Pointer

 

 

 

Word 2

 

 

 

 

 

 

 

31

 

 

16

15

 

 

0

 

Buffer Offset

 

 

Buffer Length

 

Word 3

 

 

 

 

 

 

 

31

30

29

28

27

26

25

24

SOP

EOP

OWNER

EOQ

TDOWNCMPLT

PASSCRC

JABBER

OVERSIZE

23

22

21

20

19

18

17

16

FRAGMENT

UNDERSIZED

CONTROL

OVERRUN

CODEERROR

ALIGNERROR

CRCERROR

NOMATCH

15

 

 

 

 

 

 

0

 

 

 

Packet Length

 

 

 

SPRUEQ6–December 2007

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

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Texas Instruments TMS320DM646x manual Receive Buffer Descriptor Format

TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

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The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

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Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.