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MDIO Registers
4.2MDIO Control Register (CONTROL)
The MDIO control register (CONTROL) is shown in Figure 28 and described in Table 26.
Figure 28. MDIO Control Register (CONTROL)
31 | 30 | 29 | 28 | 24 | 23 | 21 | 20 | 19 | 18 | 17 | 16 |
IDLE | ENABLE | Rsvd | HIGHEST_USER_CHANNEL | Reserved |
| PREAMBLE | FAULT | FAULTENB | Reserved | ||
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15 |
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| 0 |
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| CLKDIV |
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LEGEND: R/W = R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect;
Table 26. MDIO Control Register (CONTROL) Field Descriptions
Bit | Field | Value | Description |
31 | IDLE |
| State machine IDLE status bit |
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| 0 | State machine is not in idle state |
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| 1 | State machine is in idle state |
30 | ENABLE |
| State machine enable control bit. If the MDIO state machine is active at the time |
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| it is disabled, it will complete the current operation before halting and setting the |
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| idle bit. |
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| 0 | Disables the MDIO state machine |
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| 1 | Enable the MDIO state machine |
29 | Reserved | 0 | Reserved |
HIGHEST_USER_CHANNEL | Highest user channel that is available in the module. It is currently set to 1. This | ||
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| implies that MDIOUserAccess1 is the highest available user access channel. |
Reserved | 0 | Reserved | |
20 | PREAMBLE |
| Preamble disable |
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| 0 | Standard MDIO preamble is used |
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| 1 | Disables this device from sending MDIO frame preambles |
19 | FAULT |
| Fault indicator. This bit is set to 1 if the MDIO pins fail to read back what the |
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| device is driving onto them. This indicates a physical layer fault and the module |
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| state machine is reset. Writing a 1 to it clears this bit, writing a 0 has no effect. |
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| 0 | No failure |
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| 1 | Physical layer fault; the MDIO state machine is reset |
18 | FAULTENB |
| Fault detect enable. This bit has to be set to 1 to enable the physical layer fault |
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| detection. |
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| 0 | Disables the physical layer fault detection |
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| 1 | Enables the physical layer fault detection |
Reserved | 0 | Reserved | |
CLKDIV | Clock Divider bits. This field specifies the division ratio between the peripheral | ||
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| clock and the frequency of MDCLK. MDCLK is disabled when CLKDIV is set to |
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| 0. MDCLK frequency = peripheral clock frequency/(CLKDIV + 1). |
72 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) |
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