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Architecture

2.9.1.3.1Collision-Based Receive Buffer Flow Control

Collision-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in half-duplex mode (the FULLDUPLEX bit is cleared in MACCONTROL). When receive flow control is enabled and triggered, the EMAC generates collisions for received frames. The jam sequence transmitted is the 12-byte sequence C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3h. The jam sequence begins no later than approximately as the source address starts to be received. Note that these forced collisions are not limited to a maximum of 16 consecutive collisions, and are independent of the normal back-off algorithm.

Receive flow control does not depend on the value of the incoming frame destination address. A collision is generated for any incoming packet, regardless of the destination address, if any EMAC enabled channel’s free buffer register value is less than or equal to the channel’s flow threshold value.

2.9.1.3.2IEEE 802.3x-Based Receive Buffer Flow Control

IEEE 802.3x-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in full-duplex mode (the FULLDUPLEX bit is set in MACCONTROL). When receive flow control is enabled and triggered, the EMAC transmits a pause frame to request that the sending station stop transmitting for the period indicated within the transmitted pause frame.

The EMAC transmits a pause frame to the reserved multicast address at the first available opportunity (immediately if currently idle or following the completion of the frame currently being transmitted). The pause frame contains the maximum possible value for the pause time (FFFFh). The EMAC counts the receive pause frame time (decrements FF00h to 0) and retransmits an outgoing pause frame, if the count reaches 0. When the flow control request is removed, the EMAC transmits a pause frame with a zero pause time to cancel the pause request.

Note that transmitted pause frames are only a request to the other end station to stop transmitting. Frames that are received during the pause interval are received normally (provided the receive FIFO is not full).

Pause frames are transmitted if enabled and triggered, regardless of whether or not the EMAC is observing the pause time period from an incoming pause frame.

The EMAC transmits pause frames as described below:

∙The 48-bit reserved multicast destination address 01.80.C2.00.00.01h.

∙The 48-bit source address (set using the MACSRCADDRLO and MACSRCADDRHI registers).

∙The 16-bit length/type field containing the value 88.08h.

∙The 16-bit pause opcode equal to 00.01h.

∙The 16-bit pause time value of FF.FFh. A pause-quantum is 512 bit-times. Pause frames sent to cancel a pause request have a pause time value of 00.00h.

∙Zero padding to 64-byte data length (EMAC transmits only 64-byte pause frames).

∙The 32-bit frame-check sequence (CRC word).

All quantities are hexadecimal and are transmitted most-significant byte first. The least-significant bit (LSB) is transferred first in each byte.

If the RXBUFFERFLOWEN bit in MACCONTROL is cleared to 0 while the pause time is nonzero, then the pause time is cleared to 0 and a zero count pause frame is sent.

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Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)

SPRUEQ6–December 2007

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Texas Instruments TMS320DM646x Collision-Based Receive Buffer Flow Control, Ieee 802.3x-Based Receive Buffer Flow Control
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TMS320DM646x specifications

The Texas Instruments TMS320DM646x series is a powerful family of digital media processors designed to handle high-performance applications in video, imaging, and audio processing. These devices leverage advanced technologies to deliver efficient processing capabilities for a variety of embedded systems, making them ideal for multimedia solutions.

At the core of the TMS320DM646x is the versatile DSP architecture, which optimizes performance for digital signal processing tasks. This architecture allows for real-time processing, enabling the devices to handle complex algorithms necessary for image and video compression, thereby meeting the rigorous demands of modern multimedia applications.

One of the standout features of the TMS320DM646x series is its dual-core architecture. This consists of a Digital Signal Processor (DSP) alongside an ARM-based application processor. The DSP is predominantly employed for critical processing tasks, allowing it to execute high-throughput data streams efficiently, while the ARM processor manages control tasks and user interfaces. This division of labor enhances overall system performance and responsiveness.

The series supports a wide range of video formats and technologies, including HD video encoding and decoding, which accommodates HD resolution content essential for today’s multimedia applications. Furthermore, the TMS320DM646x integrates hardware accelerators for video compression standards such as H.264 and MPEG-4, which significantly reduce the processing burden on the CPU, resulting in lower power consumption and higher efficiency.

Networking capabilities are another significant feature of the TMS320DM646x. With support for Ethernet, the device can handle streaming media applications and connectivity, facilitating the transmission of high-quality audio and video over the internet. This connectivity is crucial for developing robust IPTV and streaming solutions.

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Overall, the Texas Instruments TMS320DM646x series offers an exceptional combination of processing power, advanced multimedia capabilities, and energy efficiency. It optimally supports a wide array of applications, from video processing and image analysis to audio encoding. This comprehensive feature set, along with its robust architecture, positions the TMS320DM646x as a leading choice for developers in the digital media space.
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