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Ethernet Media Access Controller (EMAC) Registers
5.31 Emulation Control Register (EMCONTROL)
The emulation control register (EMCONTROL) is shown in Figure 71 and described in Table 70.
Figure 71. Emulation Control Register (EMCONTROL)
31 |
|
| 16 |
Reserved |
|
|
|
|
|
| |
15 | 2 | 1 | 0 |
Reserved |
| SOFT | FREE |
|
LEGEND: R = Read only; R/W = Read/Write;
Table 70. Emulation Control Register (EMCONTROL) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
1 | SOFT | Emulation soft bit | |
0 | FREE | Emulation free bit |
5.32 FIFO Control Register (FIFOCONTROL)
The FIFO control register (FIFOCONTROL) is shown in Figure 72 and described in Table 71.
Figure 72. FIFO Control Register (FIFOCONTROL)
31 | 23 | 22 |
| 16 |
Reserved |
|
| RXFIFOFLOWTHRESH |
|
|
|
| ||
15 |
| 5 | 4 | 0 |
Reserved |
|
| TXCELLTHRESH |
|
|
|
|
LEGEND: R/W = Read/Write; R = Read only;
Table 71. FIFO Control Register (FIFOCONTROL) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
RXFIFOFLOWTHRESH | Receive FIFO flow control threshold. Occupancy of the receive FIFO when receive | ||
|
|
| FIFO flow control is triggered (if enabled). The default value is 2h, which means that |
|
|
| receive FIFO flow control is triggered when the occupancy of the FIFO reaches 2 cells. |
Reserved | 0 | Reserved | |
TXCELLTHRESH | Transmit FIFO cell threshold. Indicates the number of | ||
|
|
| be in the transmit FIFO before the packet transfer is initiated. Packets with fewer cells |
are initiated when the complete packet is contained in the FIFO. This value must be greater than or equal to 2 and less than or equal to 24 (2 ≥ TXCELLTHRESH ≤ 24).
114 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) |
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