Texas Instruments TMS320DM646x manual Gigabit Media Independent Interface Gmii Connections, Gmtclk

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Architecture

2.3.2Gigabit Media Independent Interface (GMII) Connections

Figure 3 shows a device with integrated EMAC and MDIO interfaced via a GMII connection. This interface is available in 10 Mbps, 100 Mbps, and 1000 Mbps modes.

The GMII interface supports 10/100/1000 Mbps modes. Only full-duplex mode is available in 1000 Mbps mode. In 10/100 Mbps modes, the GMII interface acts like an MII interface and only the lower 4 bits of data are transferred for each of the data buses. The individual EMAC and MDIO signals for the GMII interface are summarized in Figure 3.

Figure 3. Ethernet Configuration—GMII Connections

System

core

EMAC

MDIO

MTCLK

GMTCLK

RFTCLK

MTXD[7−0]

MTXEN

MCOL

MCRS

MRCLK

MRXD[7−0]

MRXDV

MRXER

MDCLK

MDIO

Physical layer device (PHY)

2.5MHz,

25 MHz,

or 125 MHz

Transformer

RJ−45

		Table 2. EMAC and MDIO Signals for GMII Interface
Signal	Type	Description
MTCLK	I	Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference
		for transmit operations in 10/100 Mbps mode. The MTXD and MTXEN signals are tied to this clock
		when in 10/100 Mbps mode. The clock is generated by the PHY and is 2.5 MHZ at 10 Mbps
		operation, and 25 MHZ at 100 Mbps operation.
GMTCLK	O	GMII source synchronous transmit clock (GMTCLK). This clock is used in 1000 Mbps mode only,
		providing a continuous 125 MHZ frequency for transmit operations. The MTXD and MTXEN signals
		are tied to this clock when in Gigabit mode. The clock is generated by the EMAC and is 125 MHZ.
RFTCLK	I	Reference transmit clock (RFTCLK). The reference transmit clock is a continuous clock that provides
		the timing reference for transmit operations in 1000 Mbps mode. This 125-MHZ clock is generated
		by the PHY.
MTXD[7-0]	O	Transmit data (MTXD). The transmit data pins are a collection of 8 data signals comprising 8 bits of
		data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MTCLK in 10/100
		Mbps mode, and by GMTCLK in Gigabit mode, and valid only when MTXEN is asserted.
MTXEN	O	Transmit enable (MTXEN). The transmit enable signal indicates that the MTXD pins are generating
		nibble data for use by the PHY. It is driven synchronously to MTCLK in 10/100 Mbps mode, and to
		GMTCLK in Gigabit mode.
MCOL	I	Collision detected (MCOL). The MCOL pin is asserted by the PHY when it detects a collision on the
		network. It remains asserted while the collision condition persists. This signal is not necessarily
		synchronous to MTCLK nor MRCLK. This pin is used in half-duplex operation only.

SPRUEQ6–December 2007	Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)	17
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