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Ethernet Media Access Controller (EMAC) Registers
5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 50 and described in Table 49.
| Figure 50. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) |
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31 |
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| 16 |
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| Reserved |
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15 |
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| 8 |
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| Reserved |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX7MASK | TX6MASK | TX5MASK | TX4MASK | TX3MASK | TX2MASK | TX1MASK | TX0MASK |
LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect;
Table 49. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0 | Reserved | |
7 | TX7MASK | Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. | |
6 | TX6MASK | Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. | |
5 | TX5MASK | Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. | |
4 | TX4MASK | Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. | |
3 | TX3MASK | Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. | |
2 | TX2MASK | Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. | |
1 | TX1MASK | Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. | |
0 | TX0MASK | Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. |
94 | Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | |
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