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Ethernet Media Access Controller (EMAC) Registers
5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023)
The total number of
∙Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address
∙Did not experience late collisions, excessive collisions, underrun, or carrier sense error
∙Was
CRC errors, alignment/code errors, and overruns do not affect the recording of frames in this statistic.
5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP)
The total number of
∙Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address
∙Did not experience late collisions, excessive collisions, underrun, or carrier sense error
∙Was
CRC/alignment/code errors, underruns, and overruns do not affect frame recording in this statistic.
5.50.33 Network Octet Frames Register (NETOCTETS)
The total number of bytes of frame data received and transmitted on the EMAC. Each frame counted has all of the following:
∙Was any data or MAC control frame destined for any unicast, broadcast, or multicast address (address match does not matter)
∙Was of any size (including less than
Also counted in this statistic is:
∙Every byte transmitted before a
∙Every byte transmitted before each collision was experienced (multiple retries are counted each time)
∙Every byte received if the EMAC is in
Error conditions such as alignment errors, CRC errors, code errors, overruns, and underruns do not affect the recording of bytes in this statistic. The objective of this statistic is to give a reasonable indication of Ethernet utilization.
5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS)
The total number of frames received on the EMAC that had either a FIFO or DMA start of frame (SOF) overrun. An SOF overrun frame is defined as having all of the following:
∙Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode
∙Was of any size (including less than
∙The EMAC was unable to receive it because it did not have the resources to receive it (cell FIFO full or no DMA buffer available at the start of the frame).
CRC errors, alignment errors, and code errors have no effect on this statistic.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) | 131 |
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