Xilinx UG144 manuals
Computer Equipment > Network Card
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138 pages 1.67 Mb
2 UG144 April 24, 20093 Revision History5 Table of ContentsSchedule of Figures Schedule of Tables Preface: About This Guide Chapter 1: Introduction Chapter 2: Core Architecture Chapter 3: Generating the Core 6 Chapter 4: Designing with the CoreGeneral Design Guidelines Using the MDIO interface Chapter 5: Using the Client Side Data PathReceiving Inbound Frames Transmitting Outbound Frames Chapter 6: Using Flow ControlOverview of Flow Control Flow Control Operation of the GEMAC Flow Control Implementation Example Chapter 7: Using the Physical Side InterfaceImplementing External GMII Implementing External RGMII 7 Chapter 8: Configuration and StatusUsing the Optional Management Interface Chapter 9: Constraining the Core Chapter 10: Clocking and ResettingClocking the Core Multiple Cores Reset Conditions Chapter 11: Interfacing to Other CoresEthernet 1000Base-X PCS/PMA or SGMII Core Ethernet Statistics Core 8 Chapter 12: Implementing Your DesignAppendix A: Using the Client-Side FIFO Appendix B: Core Verification, Compliance, and Interoperability Appendix C: Calculating DCM Phase-Shifting Appendix D: Core Latency 9 Schedule of Figures13 Schedule of Tables15 About This Guide19 IntroductionAbout the Core Recommended Design Experience Additional Core Resources Related Xilinx Ethernet Products and Services 20 SpecificationsTechnical Support Feedback Chapter 2 21 Core Architecture31 Generating the Core 35 Designing with the CoreGeneral Design GuidelinesDesign StepsUsing the Example Design as a Starting Point Implementing the 1-Gigabit Ethernet MAC in Your Application 37 Know the Degree of Difficulty38 Keep it RegisteredRecognize Timing Critical Signals Use Supported Design Flows Make Only Allowed Modifications Chapter 5 39 Using the Client Side Data Path53 Using Flow Control61 Using the Physical Side InterfaceImplementing External GMIIGMII Transmitter Logic 63 GMII Receiver LogicSpartan-3, Spartan-3E, Spartan-3A and Virtex-4 DevicesChapter 7: Using the Physical Side Interface 66 Implementing External RGMIIFigure 7-4: External RGMII Transmitter Logic RGMII Transmitter LogicSpartan-3, Spartan-3E, Spartan-3A and Spartan-3A DSP DevicesIOB LOGIC 1-Gigabit Ethernet MAC Core DCM CLKIN CLK0 FB CLK90 IOB LOGIC 70 RGMII Receiver LogicSpartan-3, Spartan-3E, Spartan-3A and Spartan-3A DSP Devices 75 RGMII Inband Status Decoding LogicRGMII RECEIVER LOGIC Figure 7-10: RGMII Inband Status Decoding Logic1-Gigabit Ethernet MAC Core 76 Using the MDIO interfaceConnecting the MDIO to an Internally Integrated PHY Connecting the MDIO to an External PHY Chapter 8 77 Configuration and Status93 Constraining the Core Required Constraints Chapter 10 109 Clocking and ResettingClocking the CoreWith Internal GMII With External GMII With RGMII 110 Multiple CoresWith External GMII 111 With RGMIIChapter 10: Clocking and Resetting Figure 10-4: Clock Management Logic with External RGMII (Multiple Cores) Figure 10-5: Reset Circuit for a Single Clock/reset Domain 112 Reset ConditionsChapter 11 113 Interfacing to Other CoresEthernet 1000Base-X PCS/PMA or SGMII Core 119 Ethernet Statistics CoreConnecting the Ethernet Statistics Core to Provide Statistics Gathering Chapter 12 123 Implementing Your Design127 Using the Client-Side FIFO133 Core Verification, Compliance, and InteroperabilityVerification by Simulation Hardware Verification Appendix C 135 Calculating DCM Phase-ShiftingDCM Phase-Shifting Finding the Ideal Phase-Shift Appendix D 137 Core LatencyTransmit Path Latency Receive Path Latency
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