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Chapter 5: Using the Client Side Data Path

Client-Supplied FCS Passing

If the GEMAC core is configured to pass the FCS field to the client (see “Configuration Registers,” on page 78), this is handled as shown in Figure 5-3. In this case, any padding inserted into the frame to meet Ethernet minimum frame length specifications will be left intact and passed to the client.

Even though the FCS is passed up to the client, it is also verified by the GEMAC core, and rx_bad_frame asserted if the FCS check fails.

gmii_rx_clk

rx_data[7:0]

DA

SA

L/T

DATA

FCS

rx_data_valid

rx_good_frame

rx_bad_frame

Figure 5-3:Frame Reception with In-Band FCS Field

VLAN Tagged Frames

Figure 5-4illustrates the reception of a VLAN tagged frame (if enabled). The VLAN frame is passed to the client so that the frame may be identified as VLAN tagged. This is followed by the Tag Control Information bytes, V1 and V2. More information on the interpretation of these bytes may be found in IEEE 802.3-2005standard.

gmii_rx_clk

 

 

 

rx_data[7:0]

 

81 00V1V2

 

DA

SA

VLAN L/T

DATA

 

 

tag

 

rx_data_valid

rx_good_frame

rx_bad_frame

Figure 5-4:Reception of a VLAN Tagged Frame

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1-Gigabit Ethernet MAC v8.5 User Guide

 

 

UG144 April 24, 2009

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Xilinx UG144 manual Client-Supplied FCS Passing, Vlan Tagged Frames

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

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Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

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