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Chapter 9: Constraining the Core

INST *rgmii_interface/delay_rgmii_tx_clk IDELAY_TYPE = “FIXED”;

INST *rgmii_interface/delay_rgmii_tx_clk ODELAY_VALUE = 25;

INST *rgmii_interface/delay_rgmii_tx_clk DELAY_SRC = “O”;

INST *rgmii_interface/delay_rgmii_rx_ctl IDELAY_TYPE = “FIXED”;

INST *rgmii_interface/delay_rgmii_rx_ctl IDELAY_VALUE = 20;

INST *rgmii_interface/delay_rgmii_rx_ctl DELAY_SRC = “I”;

The value of IDELAY_VALUE is preconfigured in the example designs to meet the setup and hold constraints for the example RGMII pinout in the particular device. The setup/hold timing which is achieved after place-and-route is reported in the data sheet section of the TRCE report (created by the implement script).

When IDELAY or IODELAY primitives are instantiated with a fixed delay attribute, an IDELAYCTRL component must be also instantiated to continuously calibrate the individual input delay elements. The IDELAYCTRL module requires a reference clock, which is assumed to be an input to the example design delivered by CORE Generator. The most efficient way to use the IDELAYCTRL module is to lock the placement of the instance to the clock region of the device where the IDELAY/IODELAY components are placed. An example LOC constraint for the IDELAYCTRL module is shown commented-out in the UCF. See the Virtex-5 User Guide and code comments for more information.

The following constraints are provided in the example design to link the instance of the IDELAYCTRL to the IODELAY components used on the RGMII. These constraints aid the Xilinx tools in automatic IDELAYCTRL placement:

# Group IODELAY and IDELAYCTRL components to aid placement

INST "*gemac_block/rgmii_interface/delay_rgmii_rx_clk"HIODELAY_GROUP = "HIODELAY_RGMII_GRP1";

INST "*gemac_block/rgmii_interface/*delay_rgmii_rxd" HIODELAY_GROUP = "HIODELAY_RGMII_GRP1";

INST "*gemac_block/rgmii_interface/delay_rgmii_rx_ctl" HIODELAY_GROUP = "HIODELAY_RGMII_GRP1";

INST "*gemac_block/dlyctrl" IHODELAY_GROUP = "HIODELAY_RGMII_GRP1";

RGMII DDR Constraints

The following constraints are present for RGMII designs in all devices with the exception of Virtex-4 and Virtex-5 devices. Due to the use of IDDR and ODDR primitives in the Virtex-4 design, these extra clocking constraints are not required.

The RGMII design requires further clock crossing constraints to ensure timing is met when crossing from rising to falling clock edges and vice versa. A stringent time constraint ensures that timing is met with the worst-case timing allowed in the RGMII specification.

INST "*rgmii_interface/rgmii_rxd_reg_4" TNM="rgmii_falling";

INST "*rgmii_interface/rgmii_rxd_reg_5" TNM="rgmii_falling";

INST "*rgmii_interface/rgmii_rxd_reg_6" TNM="rgmii_falling";

INST "*rgmii_interface/rgmii_rxd_reg_7" TNM="rgmii_falling";

INST "*rgmii_interface/rgmii_rx_ctl_reg" TNM="rgmii_falling";

INST "*rgmii_interface/gmii_rxd_reg_4" TNM="rgmii_rising";

INST "*rgmii_interface/gmii_rxd_reg_5" TNM="rgmii_rising";

INST "*rgmii_interface/gmii_rxd_reg_6" TNM="rgmii_rising";

INST "*rgmii_interface/gmii_rxd_reg_7" TNM="rgmii_rising";

INST "*rgmii_interface/gmii_rx_er_reg" TNM="rgmii_rising"; TIMESPEC "TS_rgmii_falling_to_rising" = FROM "rgmii_falling" TO "rgmii_rising" 3200 ps;

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UG144 April 24, 2009

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Xilinx UG144 manual Rgmii DDR Constraints

UG144 specifications

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