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Xilinx UG144 manual 116

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Chapter 11: Interfacing to Other Cores

Figure 11-2illustrates the following:

•Direct internal connections are made between the GMII interfaces between the two cores.

•If the GEMAC has been generated with the optional Management Interface, the MDIO port can be connected up to that of the Ethernet 1000BASE-X PCS/PMA or SGMII core to access its embedded configuration and status registers. See “Using the Optional Management Interface.”

•Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE-X PCS/PMA or SGMII core, the entire GMII is synchronous to a single clock domain. For this reason, userclk2 is used as the 125 MHz reference clock for both cores and the transmitter and receiver logic of the GEMAC core now operate in the same clock domain. This allows clock crossing constraints between the gtx_clk and gmii_rx_clk clock domains to be removed from the GEMAC UCF. See “Timespecs for Critical Logic within the Core.”

116	www.xilinx.com	1-Gigabit Ethernet MAC v8.5 User Guide
		UG144 April 24, 2009

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Xilinx UG144 manual 116

Contents

LogiCORE IP Gigabit Ethernet MAC UG144 April 24Gigabit Ethernet MAC v8.5 User Guide Revision History Date Version RevisionDIS Product Table of Contents Designing with the Core Configuration and Status Appendix C Calculating DCM Phase-Shifting 1Block Diagram Schedule of Figures2External Gmii Receiver Logic for Spartan-3, Spartan-3E, Figure A-2Frame Transfer across LocalLink Interface DIS Product Schedule of Tables Clocking and Resetting Interfacing to Other Cores Guide Contents About This GuideConventions TypographicalPreface About This Guide Convention Meaning or Use ExampleOnline Document List of AcronymsConventions Acronym Spelled OutPreface About This Guide Acronym Spelled Out VhdlRelated Xilinx Ethernet Products and Services IntroductionAbout the Core Recommended Design ExperienceSpecifications Technical SupportFeedback Gemac CoreCore Architecture System OverviewCore Components Core Interfaces Core InterfacesGmac Core with Optional Management Interface Core Architecture Core Interfaces Client Side Interface Transmitter InterfaceReceiver Interface Flow Control InterfaceManagement Interface Optional MAC Unicast Address OptionalConfiguration Vector Optional Asynchronous Reset7Reset Signal Direction Clock Domain Description Physical Side InterfaceMdio Interface Generating the Core Graphical User InterfaceParameter Values in the XCO File Output Generation Generating the Core Using the Example Design as a Starting Point Designing with the CoreGeneral Design Guidelines Design StepsDesigning with the Core 11-Gigabit Ethernet MAC Core Example DesignGeneral Design Guidelines Know the Degree of DifficultyImplementing the 1-Gigabit Ethernet MAC in Your Application Recognize Timing Critical Signals Keep it RegisteredUse Supported Design Flows Make Only Allowed ModificationsUsing the Client Side Data Path 1Abbreviations Used in Timing Diagrams DefinitionReceiving Inbound Frames Normal Frame ReceptionUsing the Client Side Data Path Rxgoodframe, rxbadframe timingFrame Reception with Errors Receiving Inbound FramesClient-Supplied FCS Passing Vlan Tagged FramesLength/Type Field Error Checks EnabledDisabled Maximum Permitted Frame LengthReceiver Statistics Vector 5Receiver Statistics Vector TimingDIS Product Length see Maximum Permitted Frame Transmitting Outbound Frames Normal Frame TransmissionPadding Transmitting Outbound FramesClient Underrun 7Frame Transmission with Client-supplied FCSInter-Frame Gap Adjustment 9Transmission of a Vlan Tagged Frame10Inter-Frame Gap Adjustment Transmitter Statistics VectorName Bit 31 is equivalent to bit Flow Control Requirement Using Flow ControlOverview of Flow Control Using Flow Control Flow Control BasicsPause Control Frames Overview of Flow ControlFlow Control Operation of the Gemac Transmitting a Pause Control FrameCore-initiated Pause Request Client Initiated Pause RequestReceiving a Pause Control Frame Core Initiated Response to a Pause RequestClient Initiated Response to a Pause Request Flow Control Operation of the GemacFlow Control Implementation Example MethodFlow Control Implementation Example 4Flow Control Implementation Triggered from Fifo OccupancyUsing Flow Control Gmii Transmitter Logic Using the Physical Side InterfaceImplementing External Gmii Using the Physical Side Interface 1External Gmii Transmitter LogicImplementing External Gmii Gmii Receiver LogicSpartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices DCM Reset circuitry Virtex-5 Devices 3External Gmii Receiver Logic for Virtex-5 DevicesImplementing External Rgmii Rgmii Transmitter LogicVirtex-4 Devices Implementing External Rgmii5External Rgmii Transmitter Logic in Virtex-4 Devices 6External Rgmii Transmitter Logic in Virtex-5 Devices Rgmii Receiver Logic 7External Rgmii Receiver Logic Virtex-4 Devices 8External Rgmii Receiver Logic for Virtex-4 Devices 9External Rgmii Receiver Logic for Virtex-5 Devices Rgmii Inband Status Decoding Logic 10RGMII Inband Status Decoding LogicConnecting the Mdio to an External PHY Using the Mdio interfaceConnecting the Mdio to an Internally Integrated PHY Host Clock Frequency Configuration and StatusUsing the Optional Management Interface 2Configuration Registers Address Description Configuration RegistersConfiguration and Status Receiver Configuration Using the Optional Management Interface3Receiver Configuration Word Bit Default Description Receiver Configuration WordTransmitter Configuration Interframe Gap Adjust Enable If ‘1,’ the transmitter willFlow Control Configuration 6Flow Control Configuration Word Bit Default DescriptionMdio Configuration Address Filter ConfigurationWriting and Reading to and from the Configuration Registers 10Address Table Configuration Word Bits Default Description11 Address Table Configuration Word 12Address Filter Mode Bits Default Description1Configuration Register Write Timing Accessing the Address Table 3Address Table Write TimingMdio Interface Introduction to MdioWrite Transaction 5Typical MDIO-managed SystemAccessing Mdio With Gemac Read Transaction8MDIO Access through Management Interface Access without the Management Interface Pause frame MAC Source Address470Transmitter Interframe Gap Adjust Enable Receive Flow Control Enable . When this bit Constraining the Core Required ConstraintsPeriod Constraints for Clock Nets Constraining the CoreTimespecs for Critical Logic within the Core Required ConstraintsGmii IOB Constraints Constraints when Implementing an External GmiiTimespecs for Reset Logic within the Core Gmii Input Setup/Hold Timing 1Input Gmii Timing Symbol Min Max UnitsVirtex-5 Devices Non-Virtex-5 devices Understanding Timing Reports for Gmii Setup/Hold TimingVirtex-5 devices with Delayed Data/Control Virtex-5 Devices with Delayed Clock Constraints when Implementing an External Rgmii Rgmii IOB ConstraintsRgmii Input Setup/Hold Timing 2Input Rgmii Timing Symbol Min Typical UnitsSpartan-3, Spartan-3E, Spartan-3A, and Virtex-4 Devices Rgmii DDR Constraints Understanding Timing Reports for Rgmii Setup/Hold timing 106 4Timing Report Setup/Hold Illustration 108 Clocking and Resetting Clocking the CoreWith Internal Gmii With External GmiiClocking and Resetting Multiple CoresWith Rgmii Standard Clocking SchemeMultiple Cores 3Clock Management Logic with External Gmii Multiple CoresReset Conditions 4Clock Management Logic with External Rgmii Multiple CoresInterfacing to Other Cores Ethernet 1000Base-X PCS/PMA or Sgmii CoreIntegration to Provide 1000BASE-X PCS with TBI Interfacing to Other CoresEthernet 1000Base-X PCS/PMA or Sgmii Core 116 Virtex-5 LXT and SXT Devices GTPVirtex-5 FXT Devices ClkdvEthernet Statistics Core Ethernet Statistics CoreIntegration to Provide Sgmii Functionality 120 Configuration Miim access Statistics Read 122 Using the Simulation Model Implementing Your DesignPre-implementation Simulation SynthesisImplementation XST-VerilogGenerating the Xilinx Netlist Mapping the DesignPost-Implementation Simulation Placing-and-Routing the DesignStatic Timing Analysis Generating a BitstreamUsing the Model Other Implementation InformationUsing the Client-Side Fifo GMII/RGMIITransmit Fifo Appendix a Using the Client-Side FifoInterfaces Receive Fifo InterfacesOverview of LocalLink Interface Data FlowFunctional Operation Functional OperationClock Requirements Expanding Maximum Frame Size User Interface Data Width ConversionHardware Verification Core Verification, Compliance, and InteroperabilityVerification by Simulation 134 Finding the Ideal Phase-Shift Calculating DCM Phase-ShiftingDCM Phase-Shifting Appendix C Calculating DCM Phase-Shifting Receive Path Latency Core LatencyTransmit Path Latency Appendix D Core Latency