R

-- DISCONTINUED PRODUCT --

Chapter 2: Core Architecture

MDIO Interface

Table 2-9describes the MDIO Interface signals. See “Using the MDIO interface,” on page 76.

Table 2-9:MDIO Interface Signal Pinout

Signal

Direction

Clock

Description

Domain

 

 

 

 

 

 

 

mdc

Output

host_clk

Management Clock: programmable

 

 

 

frequency derived from host_clk.

 

 

 

 

mdio_in1

Input

host_clk

Input data signal for communication with

 

 

 

PHY configuration and status. Tie high if

 

 

 

unused.

 

 

 

 

mdio_out1

Output

host_clk

Output data signal for communication

 

 

 

with PHY configuration and status.

 

 

 

 

mdio_tri1

Output

host_clk

Tristate control for MDIO signals; 0 signals

 

 

 

that the value on mdio_out should be

 

 

 

asserted onto the MDIO bus.

 

 

 

 

1.mdio_in, mdio_out and mdio_tri can be connected to a Tri-state buffer to create a bi-directional mdio signal suitable for connection to an external PHY.

30

www.xilinx.com

1-Gigabit Ethernet MAC v8.5 User Guide

 

 

UG144 April 24, 2009

Page 29 Page 31
Page 30
Image 30
Xilinx UG144 manual Mdio Interface
Page 29 Page 31

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.
Top Page Image Contents