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Chapter 2: Core Architecture

All ports of the core are internal connections in FPGA fabric. An HDL example design is delivered with the core that will add IBUFs, OBUFs, and IOB flip-flops to the external signals of the Gigabit Media Independent Interface (GMII) or Reduced Gigabit Media Independent Interface (RGMII).

All clock management logic is placed in this example design, which allows for more flexibility in implementation (for example, in designs using multiple cores). This example design is provided in both VHDL and Verilog. For more information about example designs, see the 1-Gigabit Ethernet MAC Getting Started Guide.

Client Side Interface

Transmitter Interface

Table 2-1describes the client-side transmitter signals of the GEMAC core. These signals are used to transmit data from the client logic into the core. See “Transmitting Outbound Frames,” on page 47.

The Transmitter Interface is designed to be connected to internal device logic only. Attempting to add external ports to this interface will result in a breakdown of the handshaking protocol used by this interface.

Table 2-1:Transmitter Client Interface Signal Pins

Signal

Direction

Clock

Description

Domain

 

 

 

 

 

 

 

gtx_clk

Input

n/a

Clock signal provided to the core at

 

 

 

125 MHz. Tolerance must be

 

 

 

within IEEE 802.3-2005

 

 

 

specification. This clock signal is

 

 

 

used by all of the transmitter logic.

 

 

 

 

tx_data[7:0]

Input

gtx_clk

Frame data to be transmitted is

 

 

 

supplied on this port.

 

 

 

 

tx_data_valid

Input

gtx_clk

Control signal for tx_data port.

 

 

 

 

tx_ifg_delay[7:0]

Input

gtx_clk

Control signal for configurable

 

 

 

Inter Frame Gap adjustment.

 

 

 

 

tx_ack

Output

gtx_clk

Handshaking signal asserted when

 

 

 

the current data on tx_data has

 

 

 

been accepted.

 

 

 

 

tx_underrun

Input

gtx_clk

Asserted by client to force GEMAC

 

 

 

core to corrupt the current frame.

 

 

 

 

tx_statistics_vector[31:0]

Output

gtx_clk

Provides statistical information

 

 

 

about the last frame transmitted.

 

 

 

 

tx_statistics_valid

Output

gtx_clk

Asserted at end of frame

 

 

 

transmission, indicating that the

 

 

 

tx_statistics_vector is valid.

 

 

 

 

26

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1-Gigabit Ethernet MAC v8.5 User Guide

 

 

UG144 April 24, 2009

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Xilinx UG144 manual Client Side Interface, Transmitter Interface

UG144 specifications

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