Xilinx UG144 manual 6External Rgmii Transmitter Logic in Virtex-5 Devices

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Implementing External RGMII

Virtex-5 Devices

R

The same logic that is used in Figure 7-5can also be used without modification for Virtex-5 devices. However, an alternative solution has been adopted for the example design delivered with the core. Figure 7-6shows using the physical transmitter interface of the core to create an external RGMII in a Virtex-5 device. The signal names and logic shown exactly match those delivered with the example design when the RGMII is selected.

Figure 7-6also shows that the output transmitter signals are registered in the IOBs in ODDR components. These components convert the input signals into one double-data-rate signal. The ODDR outputs are passed through IODELAYs—and these can be used to adjust the relationship between the individual signals. These signals are then output through OBUFs before being driven to output pads.

IOB LOGIC	‘1’
	‘0’

IBUFG

gtx_clk

IOB LOGIC

ODDR

D1			OBUF
D2				rgmii_txc
	Q	IODELAY		OPAD

IPAD

gtx_clk_bufg

C

ODDR

IOB LOGIC

1-Gigabit Ethernet MAC Core

	gmii_txd[0]	gmii_txd_int[0]
gtx_clk	gmii_txd[4]	gmii_txd_int[4]

D1

D2 Q

C

	OBUF
		rgmii_txd[0]
IODELAY		OPAD

IOB LOGIC

gmii_tx_en gmii_tx_en_int gmii_tx_er gmii_tx_er_int

	ODDR
D1
D2	Q	IODELAY
C

OBUF

rgmii_tx_ctl

OPAD

Figure 7-6:External RGMII Transmitter Logic in Virtex-5 Devices

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 69

UG144 April 24, 2009