UG144 April 24
LogiCORE IP Gigabit Ethernet MAC
 Gigabit Ethernet MAC v8.5 User Guide
 Date Version Revision
Revision History
 DIS Product
 Table of Contents
 Designing with the Core
 Configuration and Status
 Appendix C Calculating DCM Phase-Shifting
 Schedule of Figures
1Block Diagram
 2External Gmii Receiver Logic for Spartan-3, Spartan-3E,
 Figure A-2Frame Transfer across LocalLink Interface
 DIS Product
 Schedule of Tables
 Clocking and Resetting Interfacing to Other Cores
 About This Guide
Guide Contents
 Convention Meaning or Use Example
Conventions
Typographical
Preface About This Guide
 Acronym Spelled Out
Online Document
List of Acronyms
Conventions
 Vhdl
Preface About This Guide Acronym Spelled Out
 Recommended Design Experience
Related Xilinx Ethernet Products and Services
Introduction
About the Core
 Gemac Core
Specifications
Technical Support
Feedback
 System Overview
Core Architecture
 Core Components
 Core Interfaces
Gmac Core with Optional Management Interface
Core Interfaces
 Core Architecture
 Core Interfaces
 Transmitter Interface
Client Side Interface
 Flow Control Interface
Receiver Interface
 MAC Unicast Address Optional
Management Interface Optional
 Physical Side Interface
Configuration Vector Optional
Asynchronous Reset
7Reset Signal Direction Clock Domain Description
 Mdio Interface
 Graphical User Interface
Generating the Core
 Parameter Values in the XCO File
 Output Generation
 Generating the Core
 Design Steps
Using the Example Design as a Starting Point
Designing with the Core
General Design Guidelines
 11-Gigabit Ethernet MAC Core Example Design
Designing with the Core
 Know the Degree of Difficulty
Implementing the 1-Gigabit Ethernet MAC in Your Application
General Design Guidelines
 Make Only Allowed Modifications
Recognize Timing Critical Signals
Keep it Registered
Use Supported Design Flows
 Normal Frame Reception
Using the Client Side Data Path
1Abbreviations Used in Timing Diagrams Definition
Receiving Inbound Frames
 Rxgoodframe, rxbadframe timing
Using the Client Side Data Path
 Receiving Inbound Frames
Frame Reception with Errors
 Vlan Tagged Frames
Client-Supplied FCS Passing
 Maximum Permitted Frame Length
Length/Type Field Error Checks
Enabled
Disabled
 5Receiver Statistics Vector Timing
Receiver Statistics Vector
 DIS Product
 Length see Maximum Permitted Frame
 Transmitting Outbound Frames
Transmitting Outbound Frames
Normal Frame Transmission
Padding
 7Frame Transmission with Client-supplied FCS
Client Underrun
 9Transmission of a Vlan Tagged Frame
Inter-Frame Gap Adjustment
 Transmitter Statistics Vector
10Inter-Frame Gap Adjustment
 Name
 Bit 31 is equivalent to bit
 Using Flow Control
Overview of Flow Control
Flow Control Requirement
 Flow Control Basics
Using Flow Control
 Overview of Flow Control
Pause Control Frames
 Client Initiated Pause Request
Flow Control Operation of the Gemac
Transmitting a Pause Control Frame
Core-initiated Pause Request
 Flow Control Operation of the Gemac
Receiving a Pause Control Frame
Core Initiated Response to a Pause Request
Client Initiated Response to a Pause Request
 Method
Flow Control Implementation Example
 4Flow Control Implementation Triggered from Fifo Occupancy
Flow Control Implementation Example
 Using Flow Control
 Using the Physical Side Interface
Implementing External Gmii
Gmii Transmitter Logic
 1External Gmii Transmitter Logic
Using the Physical Side Interface
 Gmii Receiver Logic
Spartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices
Implementing External Gmii
 DCM Reset circuitry
 3External Gmii Receiver Logic for Virtex-5 Devices
Virtex-5 Devices
 Rgmii Transmitter Logic
Implementing External Rgmii
 Implementing External Rgmii
Virtex-4 Devices
 5External Rgmii Transmitter Logic in Virtex-4 Devices
 6External Rgmii Transmitter Logic in Virtex-5 Devices
 Rgmii Receiver Logic
 7External Rgmii Receiver Logic
 Virtex-4 Devices
 8External Rgmii Receiver Logic for Virtex-4 Devices
 9External Rgmii Receiver Logic for Virtex-5 Devices
 10RGMII Inband Status Decoding Logic
Rgmii Inband Status Decoding Logic
 Using the Mdio interface
Connecting the Mdio to an Internally Integrated PHY
Connecting the Mdio to an External PHY
 Configuration and Status
Using the Optional Management Interface
Host Clock Frequency
 Configuration Registers
Configuration and Status
2Configuration Registers Address Description
 Receiver Configuration Word
Receiver Configuration
Using the Optional Management Interface
3Receiver Configuration Word Bit Default Description
 Interframe Gap Adjust Enable If ‘1,’ the transmitter will
Transmitter Configuration
 6Flow Control Configuration Word Bit Default Description
Flow Control Configuration
 Address Filter Configuration
Mdio Configuration
 12Address Filter Mode Bits Default Description
Writing and Reading to and from the Configuration Registers
10Address Table Configuration Word Bits Default Description
11 Address Table Configuration Word
 1Configuration Register Write Timing
 3Address Table Write Timing
Accessing the Address Table
 Introduction to Mdio
Mdio Interface
 5Typical MDIO-managed System
Write Transaction
 Read Transaction
Accessing Mdio With Gemac
 8MDIO Access through Management Interface
 Pause frame MAC Source Address470
Access without the Management Interface
 Transmitter Interframe Gap Adjust Enable
 Receive Flow Control Enable . When this bit
 Required Constraints
Constraining the Core
 Constraining the Core
Period Constraints for Clock Nets
 Required Constraints
Timespecs for Critical Logic within the Core
 Constraints when Implementing an External Gmii
Timespecs for Reset Logic within the Core
Gmii IOB Constraints
 1Input Gmii Timing Symbol Min Max Units
Gmii Input Setup/Hold Timing
 Virtex-5 Devices
 Understanding Timing Reports for Gmii Setup/Hold Timing
Virtex-5 devices with Delayed Data/Control
Non-Virtex-5 devices
 Virtex-5 Devices with Delayed Clock
 Rgmii IOB Constraints
Constraints when Implementing an External Rgmii
 2Input Rgmii Timing Symbol Min Typical Units
Rgmii Input Setup/Hold Timing
 Spartan-3, Spartan-3E, Spartan-3A, and Virtex-4 Devices
 Rgmii DDR Constraints
 Understanding Timing Reports for Rgmii Setup/Hold timing
 106
 4Timing Report Setup/Hold Illustration
 108
 With External Gmii
Clocking and Resetting
Clocking the Core
With Internal Gmii
 Standard Clocking Scheme
Clocking and Resetting
Multiple Cores
With Rgmii
 3Clock Management Logic with External Gmii Multiple Cores
Multiple Cores
 4Clock Management Logic with External Rgmii Multiple Cores
Reset Conditions
 Ethernet 1000Base-X PCS/PMA or Sgmii Core
Interfacing to Other Cores
 Interfacing to Other Cores
Integration to Provide 1000BASE-X PCS with TBI
 Ethernet 1000Base-X PCS/PMA or Sgmii Core
 116
 GTP
Virtex-5 LXT and SXT Devices
 Clkdv
Virtex-5 FXT Devices
 Ethernet Statistics Core
Integration to Provide Sgmii Functionality
Ethernet Statistics Core
 120
 Configuration Miim access Statistics Read
 122
 Synthesis
Using the Simulation Model
Implementing Your Design
Pre-implementation Simulation
 Mapping the Design
Implementation
XST-Verilog
Generating the Xilinx Netlist
 Generating a Bitstream
Post-Implementation Simulation
Placing-and-Routing the Design
Static Timing Analysis
 Other Implementation Information
Using the Model
 GMII/RGMII
Using the Client-Side Fifo
 Appendix a Using the Client-Side Fifo
Interfaces
Transmit Fifo
 Interfaces
Receive Fifo
 Data Flow
Overview of LocalLink Interface
 Functional Operation
Clock Requirements
Functional Operation
 User Interface Data Width Conversion
Expanding Maximum Frame Size
 Core Verification, Compliance, and Interoperability
Verification by Simulation
Hardware Verification
 134
 Calculating DCM Phase-Shifting
DCM Phase-Shifting
Finding the Ideal Phase-Shift
 Appendix C Calculating DCM Phase-Shifting
 Core Latency
Transmit Path Latency
Receive Path Latency
 Appendix D Core Latency