R

-- DISCONTINUED PRODUCT --

Chapter 6: Using Flow Control

Flow Control Operation of the GEMAC

Transmitting a PAUSE Control Frame

Core-initiated Pause Request

If the GEMAC core is configured to support transmit flow control, the client can initiate a pause control frame by asserting pause_req (see “Flow Control Configuration,” on page 81). Figure 6-3illustrates pause request timing.

gtx_clk

pause_req

pause_val[15:0]

Figure 6-3:Pause Request Timing

This action causes the core to construct and transmit a pause control frame on the link with the following MAC Control frame parameters (Figure 6-2):

•The destination address used is an IEEE802.3 globally assigned multicast address (to which any flow control-capable MAC will respond).

•The source address used is the configurable pause frame MAC address (see“Receiver Configuration,” on page 79).

•The value sampled from the pause_val[15:0] port at the time of the pause_req assertion will be encoded into the MAC control parameter field to select the duration of the pause (in units of pause_quantum).

If the transmitter is inactive at the time of the pause request, this pause control frame is transmitted immediately. If the transmitter is currently busy, the current frame being transmitted is allowed to complete, followed by the pause control frame (in preference to any pending client-supplied frame).

A pause control frame initiated by this method is transmitted even if the transmitter has ceased in response to receiving an inbound pause request.

Note: Only a single pause control frame request is stored by the transmitter. if pause_req is asserted numerous times in a short time period (before the control pause frame transmission has begun), only a single pause control frame is transmitted. The most recent value sampled will be the pause_val[15:0] value used.

Client Initiated Pause Request

For maximum flexibility, flow control logic can be disabled in the core and alternatively implemented in the client logic connected to the core (see “Flow Control Configuration,” on page 81). Any type of control frame can be transmitted through the core through the client interface using the same transmission procedure as a standard Ethernet frame (see “Transmitting Outbound Frames,” on page 47).

56

www.xilinx.com

1-Gigabit Ethernet MAC v8.5 User Guide

 

 

UG144 April 24, 2009

Page 55 Page 57
Page 56
Image 56
Xilinx UG144 manual Flow Control Operation of the Gemac, Transmitting a Pause Control Frame, Core-initiated Pause Request
Page 55 Page 57

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.
Top Page Image Contents