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UG144 April 24, 2009
Revision History
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Table of Contents
Schedule of Figures Schedule of Tables Preface: About This Guide
Chapter 1: Introduction
Chapter 2: Core Architecture
Chapter 3: Generating the Core
Chapter 4: Designing with the Core
General Design Guidelines
Using the MDIO interface
Chapter 5: Using the Client Side Data Path
Receiving Inbound Frames
Chapter 8: Configuration and Status
Using the Optional Management Interface
Chapter 9: Constraining the Core
Required Constraints
Chapter 10: Clocking and Resetting
Chapter 12: Implementing Your Design
Appendix A: Using the Client-Side FIFO
Appendix B: Core Verification, Compliance, and Interoperability
Appendix C: Calculating DCM Phase-Shifting
Appendix D: Core Latency
Schedule of Figures
Chapter 7: Using the Physical Side Interface
Chapter 8: Configuration and Status
Chapter 9: Constraining the Core
Chapter 10: Clocking and Resetting
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Schedule of Tables
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Preface
About This Guide
Guide Contents
Conventions
Typographical
Online Document
List of Acronyms
The following table describes acronyms used in this manual.
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Chapter 1
Introduction
About the Core
Recommended Design Experience
Additional Core Resources
Related Xilinx Ethernet Products and Services
Specifications
Technical Support
Feedback
GEMAC Core
Document
Core Architecture
System Overview
Core Components
Transmit Engine
Receive Engine
Flow Control
Address Filter
Core Interfaces
Client Side Interface Physical Side Interface (GMII)
host_clk domain
Figure 2-2: Component Pinout for MAC with Optional Management Interface
GMAC Core with Optional Management Interface
GMAC Core Without Management Interface and With Address Filter
Core Interfaces
GEMAC Core Without Management Interface and Without Address Filter
Client Side Interface
Transmitter Interface
Receiver Interface
Flow Control Interface
Management Interface (Optional)
MAC Unicast Address (Optional)
Configuration Vector (Optional)
Asynchronous Reset
Physical Side Interface
GMII
MDIO Interface
Chapter 3
Generating the Core
Graphical User Interface
Component Name
Management Interface
Address Filter
Parameter Values in the XCO File
Output Generation
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Chapter 4
Designing with the Core
General Design Guidelines
Design Steps
Using the Example Design as a Starting Point
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Implementing the 1-Gigabit Ethernet MAC in Your Application
Know the Degree of Difficulty
Keep it Registered
Recognize Timing Critical Signals
Use Supported Design Flows
Make Only Allowed Modifications
Chapter 5
Using the Client Side Data Path
Receiving Inbound Frames
Normal Frame Reception
rx_good_frame, rx_bad_frame timing
Frame Reception with Errors
Client-Supplied FCS Passing
VLAN Tagged Frames
Maximum Permitted Frame Length
Length/Type Field Error Checks
Enabled
Disabled
Address Filter
Receiver Statistics Vector
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Transmitting Outbound Frames
Normal Frame Transmission
Paddin g
Client-Supplied FCS Passing
Client Underrun
VLAN Tagged Frames
Maximum Permitted Frame Length
Inter-Frame Gap Adjustment
Transmitter Statistics Vector
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Chapter 6
Using Flow Control
Overview of Flow Control
Flow Control Requirement
Flow Control Basics
Pause Control Frames
Flow Control Operation of the GEMAC
Transmitting a PAUSE Control Frame
Core-initiated Pause Request
Client Initiated Pause Request
Receiving a Pause Control Frame
Core Initiated Response to a Pause Request
Pause Frame Reception Disabled
Pause Frame Reception Enabled
Client Initiated Response to a Pause Request
Flow Control Implementation Example
Method
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Chapter 7
Using the Physical Side Interface
Implementing External GMII
GMII Transmitter Logic
Chapter 7: Using the Physical Side Interface
Figure 7-1: External GMII Transmitter Logic
GMII Receiver Logic
Spartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices
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Chapter 7: Using the Physical Side Interface
Implementing External RGMII
Figure 7-4: External RGMII Transmitter Logic
RGMII Transmitter Logic
Spartan-3, Spartan-3E, Spartan-3A and Spartan-3A DSP Devices
IOB LOGIC
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RGMII Receiver Logic
Spartan-3, Spartan-3E, Spartan-3A and Spartan-3A DSP Devices
Figure 7-7: External RGMII Receiver Logic
IOB LOGIC
1-Gigabit Ethernet MAC Core
DCM CLKIN CLK0 FB
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Figure 7-8: External RGMII Receiver Logic for Virtex-4 Devices
1-Gigabit Ethernet MAC Core
DCM CLKIN CLK0 FB
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RGMII Inband Status Decoding Logic
RGMII RECEIVER LOGIC
Figure 7-10: RGMII Inband Status Decoding Logic
1-Gigabit Ethernet MAC Core
Using the MDIO interface
Connecting the MDIO to an Internally Integrated PHY
Connecting the MDIO to an External PHY
Chapter 8
Configuration and Status
Using the Optional Management Interface
Host Clock Frequency
Configuration Registers
Receiver Configuration
Transmitter Configuration
Flow Control Configuration
MDIO Configuration
Address Filter Configuration
Writing and Reading to and from the Configuration Registers
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Accessing the Address Table
MDIO Interface
Introduction to MDIO
Abbreviations Used
Write Transaction
Read Transaction
Accessing MDIO With GEMAC
--------------------------------------------------------------------=
f
f 1 Clock Divide[4:0]+()2
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Access without the Management Interface
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Chapter 9
Constraining the Core
Required Constraints
Device, Package, and Speedgrade Selection
I/O Location Constraints
Placement Constraints
PERIOD Constraints for Clock Nets
gtx_clk
gmii_rx_clk (for GMII Example Designs)
rgmii_rxc (for RGMII Example Designs)
host_clk
Timespecs for Critical Logic within the Core
Flow Control
Configuration
Timespecs for Reset Logic within the Core
Constraints when Implementing an External GMII
GMII IOB Constraints
GMII Input Setup/Hold Timing
Spartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices
Virtex-5 Devices
Understanding Timing Reports for GMII Setup/Hold Timing
Non-Virtex-5 devices
Virtex-5 devices with Delayed Data/Control
Virtex-5 Devices with Delayed Clock
Constraints when Implementing an External RGMII
RGMII IOB Constraints
= 8 - 6.134 = 1.866 ns
= 7.554 - 8 = -0.446 ns
RGMII Input Setup/Hold Timing
Spartan-3, Spartan-3E, Spartan-3A, and Virtex-4 Devices
Virtex-5 Devices
RGMII DDR Constraints
Understanding Timing Reports for RGMII Setup/Hold timing
Non-Virtex-5 Devices
Virtex-5 devices with delayed Data/Control
Virtex-5 Devices with Delayed Clock
= 8 - 7.179 = 0.821 ns
= 8.893 - 8 = 0.893 ns
= 0.893 ns tSETUP = 12 - 11.179 = 0.821 ns
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Chapter 10
Clocking and Resetting
Clocking the Core
With Internal GMII
With External GMII
With RGMII
Multiple Cores
With External GMII
With RGMII
Chapter 10: Clocking and Resetting
Figure 10-4: Clock Management Logic with External RGMII (Multiple Cores)
Figure 10-5: Reset Circuit for a Single Clock/reset Domain
Reset Conditions
Chapter 11
Interfacing to Other Cores
Ethernet 1000Base-X PCS/PMA or SGMII Core
Integration to Provide 1000BASE-X PCS with TBI
Ethernet 1000Base-X PCS/PMA or SGMII Core
Integration to Provide 1000BASE-X PCS and PMA using a RocketIO Tra n s c e i v e r
1-Gigabit Ethernet MAC LogiCORE
Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE
Virtex-4 GT11 RocketIO
0 0
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Virtex-5 LXT and SXT Devices
Chapter 11: Interfacing to Other Cores
Virtex-5 FXT Devices
Integration to Provide SGMII Functionality
Ethernet Statistics Core
Connecting the Ethernet Statistics Core to Provide Statistics Gathering
Chapter 11: Interfacing to Other Cores
Figure11-5 illustrates connecting the Ethernet Statistics core to the MAC.
Figure 11-5: Interfacing the Ethernet Statistics to the 1-Gigabit Ethernet MAC
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Chapter 12
Implementing Your Design
Pre-implementation Simulation
Using the Simulation Model
Synthesis
XSTVHDL
Implementation
Generating the Xilinx Netlist
Mapping the Design
Placing-and-Routing the Design
Static Timing Analysis
Post-Implementation Simulation
Generating a Simulation Model
Using the Model
Other Implementation Information
Appendix A
Using the Client-Side FIFO
Interfaces
Tra ns mit FI FO
Receive FIFO
Overview of LocalLink Interface
Data Flow
Functional Operation
Clock Requirements
Receive FIFO
Tra ns mit FI FO
VHDL
Expanding Maximum Frame Size
User Interface Data Width Conversion
Appendix B
Core Verification, Compliance, and Interoperability
Verification by Simulation
Hardware Verification
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Appendix C
Calculating DCM Phase-Shifting
DCM Phase-Shifting
Finding the Ideal Phase-Shift
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Appendix D
Core Latency
Transmit Path Latency
Receive Path Latency