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Xilinx UG144 manual 134

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Appendix B: Core Verification, Compliance, and Interoperability

134	www.xilinx.com	1-Gigabit Ethernet MAC v8.5 User Guide
		UG144 April 24, 2009

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Xilinx UG144 manual 134

Contents

LogiCORE IP Gigabit Ethernet MAC UG144 April 24Gigabit Ethernet MAC v8.5 User Guide Revision History Date Version RevisionDIS Product Table of Contents Designing with the Core Configuration and Status Appendix C Calculating DCM Phase-Shifting 1Block Diagram Schedule of Figures2External Gmii Receiver Logic for Spartan-3, Spartan-3E, Figure A-2Frame Transfer across LocalLink Interface DIS Product Schedule of Tables Clocking and Resetting Interfacing to Other Cores Guide Contents About This GuidePreface About This Guide ConventionsTypographical Convention Meaning or Use ExampleConventions Online DocumentList of Acronyms Acronym Spelled OutPreface About This Guide Acronym Spelled Out VhdlAbout the Core Related Xilinx Ethernet Products and ServicesIntroduction Recommended Design ExperienceFeedback SpecificationsTechnical Support Gemac CoreCore Architecture System OverviewCore Components Core Interfaces Core InterfacesGmac Core with Optional Management Interface Core Architecture Core Interfaces Client Side Interface Transmitter InterfaceReceiver Interface Flow Control InterfaceManagement Interface Optional MAC Unicast Address Optional7Reset Signal Direction Clock Domain Description Configuration Vector OptionalAsynchronous Reset Physical Side InterfaceMdio Interface Generating the Core Graphical User InterfaceParameter Values in the XCO File Output Generation Generating the Core General Design Guidelines Using the Example Design as a Starting PointDesigning with the Core Design StepsDesigning with the Core 11-Gigabit Ethernet MAC Core Example DesignGeneral Design Guidelines Know the Degree of DifficultyImplementing the 1-Gigabit Ethernet MAC in Your Application Use Supported Design Flows Recognize Timing Critical SignalsKeep it Registered Make Only Allowed ModificationsReceiving Inbound Frames Using the Client Side Data Path1Abbreviations Used in Timing Diagrams Definition Normal Frame ReceptionUsing the Client Side Data Path Rxgoodframe, rxbadframe timingFrame Reception with Errors Receiving Inbound FramesClient-Supplied FCS Passing Vlan Tagged FramesDisabled Length/Type Field Error ChecksEnabled Maximum Permitted Frame LengthReceiver Statistics Vector 5Receiver Statistics Vector TimingDIS Product Length see Maximum Permitted Frame Padding Transmitting Outbound FramesNormal Frame Transmission Transmitting Outbound FramesClient Underrun 7Frame Transmission with Client-supplied FCSInter-Frame Gap Adjustment 9Transmission of a Vlan Tagged Frame10Inter-Frame Gap Adjustment Transmitter Statistics VectorName Bit 31 is equivalent to bit Flow Control Requirement Using Flow ControlOverview of Flow Control Using Flow Control Flow Control BasicsPause Control Frames Overview of Flow ControlCore-initiated Pause Request Flow Control Operation of the GemacTransmitting a Pause Control Frame Client Initiated Pause RequestClient Initiated Response to a Pause Request Receiving a Pause Control FrameCore Initiated Response to a Pause Request Flow Control Operation of the GemacFlow Control Implementation Example MethodFlow Control Implementation Example 4Flow Control Implementation Triggered from Fifo OccupancyUsing Flow Control Gmii Transmitter Logic Using the Physical Side InterfaceImplementing External Gmii Using the Physical Side Interface 1External Gmii Transmitter LogicImplementing External Gmii Gmii Receiver LogicSpartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices DCM Reset circuitry Virtex-5 Devices 3External Gmii Receiver Logic for Virtex-5 DevicesImplementing External Rgmii Rgmii Transmitter LogicVirtex-4 Devices Implementing External Rgmii5External Rgmii Transmitter Logic in Virtex-4 Devices 6External Rgmii Transmitter Logic in Virtex-5 Devices Rgmii Receiver Logic 7External Rgmii Receiver Logic Virtex-4 Devices 8External Rgmii Receiver Logic for Virtex-4 Devices 9External Rgmii Receiver Logic for Virtex-5 Devices Rgmii Inband Status Decoding Logic 10RGMII Inband Status Decoding LogicConnecting the Mdio to an External PHY Using the Mdio interfaceConnecting the Mdio to an Internally Integrated PHY Host Clock Frequency Configuration and StatusUsing the Optional Management Interface 2Configuration Registers Address Description Configuration RegistersConfiguration and Status 3Receiver Configuration Word Bit Default Description Receiver ConfigurationUsing the Optional Management Interface Receiver Configuration WordTransmitter Configuration Interframe Gap Adjust Enable If ‘1,’ the transmitter willFlow Control Configuration 6Flow Control Configuration Word Bit Default DescriptionMdio Configuration Address Filter Configuration11 Address Table Configuration Word Writing and Reading to and from the Configuration Registers10Address Table Configuration Word Bits Default Description 12Address Filter Mode Bits Default Description1Configuration Register Write Timing Accessing the Address Table 3Address Table Write TimingMdio Interface Introduction to MdioWrite Transaction 5Typical MDIO-managed SystemAccessing Mdio With Gemac Read Transaction8MDIO Access through Management Interface Access without the Management Interface Pause frame MAC Source Address470Transmitter Interframe Gap Adjust Enable Receive Flow Control Enable . When this bit Constraining the Core Required ConstraintsPeriod Constraints for Clock Nets Constraining the CoreTimespecs for Critical Logic within the Core Required ConstraintsGmii IOB Constraints Constraints when Implementing an External GmiiTimespecs for Reset Logic within the Core Gmii Input Setup/Hold Timing 1Input Gmii Timing Symbol Min Max UnitsVirtex-5 Devices Non-Virtex-5 devices Understanding Timing Reports for Gmii Setup/Hold TimingVirtex-5 devices with Delayed Data/Control Virtex-5 Devices with Delayed Clock Constraints when Implementing an External Rgmii Rgmii IOB ConstraintsRgmii Input Setup/Hold Timing 2Input Rgmii Timing Symbol Min Typical UnitsSpartan-3, Spartan-3E, Spartan-3A, and Virtex-4 Devices Rgmii DDR Constraints Understanding Timing Reports for Rgmii Setup/Hold timing 106 4Timing Report Setup/Hold Illustration 108 With Internal Gmii Clocking and ResettingClocking the Core With External GmiiWith Rgmii Clocking and ResettingMultiple Cores Standard Clocking SchemeMultiple Cores 3Clock Management Logic with External Gmii Multiple CoresReset Conditions 4Clock Management Logic with External Rgmii Multiple CoresInterfacing to Other Cores Ethernet 1000Base-X PCS/PMA or Sgmii CoreIntegration to Provide 1000BASE-X PCS with TBI Interfacing to Other CoresEthernet 1000Base-X PCS/PMA or Sgmii Core 116 Virtex-5 LXT and SXT Devices GTPVirtex-5 FXT Devices ClkdvEthernet Statistics Core Ethernet Statistics CoreIntegration to Provide Sgmii Functionality 120 Configuration Miim access Statistics Read 122 Pre-implementation Simulation Using the Simulation ModelImplementing Your Design SynthesisGenerating the Xilinx Netlist ImplementationXST-Verilog Mapping the DesignStatic Timing Analysis Post-Implementation SimulationPlacing-and-Routing the Design Generating a BitstreamUsing the Model Other Implementation InformationUsing the Client-Side Fifo GMII/RGMIITransmit Fifo Appendix a Using the Client-Side FifoInterfaces Receive Fifo InterfacesOverview of LocalLink Interface Data FlowFunctional Operation Functional OperationClock Requirements Expanding Maximum Frame Size User Interface Data Width ConversionHardware Verification Core Verification, Compliance, and InteroperabilityVerification by Simulation 134 Finding the Ideal Phase-Shift Calculating DCM Phase-ShiftingDCM Phase-Shifting Appendix C Calculating DCM Phase-Shifting Receive Path Latency Core LatencyTransmit Path Latency Appendix D Core Latency