-- DISCONTINUED PRODUCT --

Flow Control Operation of the GEMAC

R

Receiving a Pause Control Frame

Core Initiated Response to a Pause Request

An error free control frame is a received frame matching the format of Figure 6-2. It must pass all standard receiver frame checks (for example, FCS field checking). In addition, the control frame received must be exactly 64-bytes in length (from destination address through to the FCS field inclusive: this is minimum legal Ethernet MAC frame size and the defined size for control frames).

Any control frame received that does passed to the receiver client with the

not conform to these checks contains an error and is rx_bad_frame signal asserted.

Pause Frame Reception Disabled

When pause control reception is disabled, an error free control frame is received through the client interface with rx_good_frame asserted (see “Flow Control Configuration,” on page 81). In this way, the frame is passed to the client logic for interpretation (see “Client Initiated Response to a Pause Request,” on page 57).

Pause Frame Reception Enabled

When pause control reception is enabled, and an error-free frame is received by the GEMAC core (see “Flow Control Configuration,” on page 81), the following frame decoding functions are performed:

The destination address field is matched against the IEEE 802.3 globally assigned multicast address or the configurable pause frame MAC address (see “Configuration Registers,” on page 78).

The length/type field is matched against the MAC control type code.

The opcode field contents are matched against the Pause opcode.

If any of the previously described checks are false, the frame is ignored by the Flow Control logic and passed up to the client logic for interpretation by marking it with rx_good_frame asserted. It is then the responsibility of the MAC client logic to decode, act on (if required), and drop this control frame.

If all the previously described checks are true, the 16-bit binary value in the MAC Control Parameters field of the control frame is then used to inhibit transmitter operation for the required number of pause_quantum. This inhibit is implemented by delaying the assertion of tx_ack at the transmitter client interface until the requested pause duration has expired. The received pause frame is then passed on to the client with rx_bad_frame asserted to indicate to the client that the pause frame can be dropped.

Note: Any frame in which the length/type field contains the MAC control type should be dropped by the receiver client logic. All control frames are indicated by rx_statistic_vector bit 19 (see “Receiver Statistics Vector,” on page 44).

Client Initiated Response to a Pause Request

For maximum flexibility, flow control logic can be disabled in the core and alternatively implemented in the client logic connected to the core (see “Flow Control Configuration,” on page 81). Any type of error-free control frame is then passed through the core with rx_good_frame asserted. The frame is passed to the client for interpretation. It is then the responsibility of the client to drop this control frame and to act on it by ceasing transmission through the core, if applicable.

1-Gigabit Ethernet MAC v8.5 User Guide

www.xilinx.com

57

UG144 April 24, 2009

Page 57
Image 57
Xilinx UG144 manual Receiving a Pause Control Frame, Core Initiated Response to a Pause Request

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.