Xilinx UG144 manual Receive Flow Control Enable . When this bit

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Chapter 8: Configuration and Status

Table 8-13:Configuration Vector Bit Definition (Continued)

	Configuration
Bit(s)	Register cross	Clock	Description
	reference
62	“Flow Control	gtx_clk	Receive Flow Control Enable. When this bit
	Configuration		is ‘1,’ received flow control frames will inhibit
	Word” bit 30		the transmitter operation. When at ‘0,’
			received flow frames are passed up to the
			client.
63	“Receiver	gtx_clk	Length/Type Error Check Disable. When
	Configuration		this bit is set to ‘1,’ the core will not perform
	Word 1” bit 25		the length/type field error checks as
			described in “Length/Type Field Error
			Checks,” on page 43. When this bit is set to
			‘0,’ the length/type field checks will be
			performed: this is normal operation.
64	“Address Filter	gmii_rx_clk	Address Filter Enable. When this bit is ‘0,’
	Mode” bit 31		the Address Filter is enabled. If it is set to ‘1,’
			the Address Filter will operate in
			promiscuous mode.
66:65	n/a	n/a	This input is unused.
67	“Receiver	gtx_clk	Control Frame Length Check Disable When
	Configuration		this bit is set to ‘1,’ the core will not mark
	Word 1” bit 24		control frames as ‘bad’ if they are greater than
			the minimum frame length.

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		UG144 April 24, 2009