Virtex-5 Devices with Delayed Clock

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Chapter 9: Constraining the Core

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to		clock gmii_rx_clk
------------	+	------------	+------------	+------------------	+--------	+
		Setup to	Hold to		Clock
Source		clk (edge)	clk (edge)	Internal Clock(s) Phase
------------	+	------------	+------------	+------------------	+--------	+

gmii_rx_dv	1.955(R)	-0.017(R) gmii_rx_clk_bufg		0.000
gmii_rx_er	1.962(R)	-0.031(R) gmii_rx_clk_bufg		0.000
gmii_rxd<0>	1.949(R)	-0.013(R) gmii_rx_clk_bufg		0.000
gmii_rxd<1>	1.944(R)	-0.009(R) gmii_rx_clk_bufg		0.000
gmii_rxd<2>	1.947(R)	-0.012(R) gmii_rx_clk_bufg		0.000
gmii_rxd<3>	1.942(R)	-0.008(R) gmii_rx_clk_bufg		0.000
gmii_rxd<4>	1.950(R)	-0.015(R) gmii_rx_clk_bufg		0.000
gmii_rxd<5>	1.962(R)	-0.026(R) gmii_rx_clk_bufg		0.000
gmii_rxd<6>	1.957(R)	-0.022(R) gmii_rx_clk_bufg		0.000
gmii_rxd<7>	1.952(R)	-0.020(R) gmii_rx_clk_bufg		0.000
------------+	------------+	------------+------------------	+	--------+

Virtex-5 Devices with Delayed Clock

Setup and Hold results for the GMII input bus can be found in the data sheet section of the Timing Report. However, depending on how the setup/hold requirements have been met, it may not be immediately obvious how the results relate to Figure 9-1. The following is an example for the GMII report from a Virtex-5 device where the clock has been delayed to meet the setup/hold requirements.

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to		clock gmii_rx_clk
------------	+	------------+	------------+------------------	+	--------	+
		Setup to	Hold to	Clock
Source		clk (edge) clk (edge) Internal Clock(s)		Phase
------------	+	------------+	------------+------------------	+	--------	+
gmii_rx_dv		-6.198(R)	7.526(R) gmii_rx_clk_bufg		0.000
gmii_rx_er		-6.225(R)	7.554(R) gmii_rx_clk_bufg		0.000
gmii_rxd<0>		-6.149(R)	7.484(R) gmii_rx_clk_bufg		0.000
gmii_rxd<1>		-6.152(R)	7.486(R) gmii_rx_clk_bufg		0.000
gmii_rxd<2>		-6.206(R)	7.532(R) gmii_rx_clk_bufg		0.000
gmii_rxd<3>		-6.207(R)	7.533(R) gmii_rx_clk_bufg		0.000
gmii_rxd<4>		-6.134(R)	7.476(R) gmii_rx_clk_bufg		0.000
gmii_rxd<5>		-6.134(R)	7.476(R) gmii_rx_clk_bufg		0.000
gmii_rxd<6>		-6.170(R)	7.506(R) gmii_rx_clk_bufg		0.000
gmii_rxd<7>		-6.170(R)	7.506(R) gmii_rx_clk_bufg		0.000
------------	+	------------+	------------+------------------	+	--------	+

The implementation requires -6.134 ns of setup. Figure 9-2illustrates that this represents a figure of 1.866 ns relative to the following rising edge of the clock (since the IDELAY has acted to delay the clock by an entire period when measured from the input flip-flop). This is less than the 2 ns required, so there is slack.

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		UG144 April 24, 2009

UG144 specifications

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Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.

Xilinx UG144 manual Virtex-5 Devices with Delayed Clock

Models: UG144

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Chapter 9: Constraining the Core

Virtex-5 Devices with Delayed Clock

1-Gigabit Ethernet MAC v8.5 User Guide

UG144 specifications