Xilinx UG144 manual Virtex-5 Devices

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Chapter 9: Constraining the Core

The fixed phase-shift is applied to the DCM using the following UCF syntax:

INST *gmii_interface/gmii_rxc_dcm CLKOUT_PHASE_SHIFT = FIXED;

INST *gmii_interface/gmii_rxc_dcm PHASE_SHIFT = 0;

The value of PHASE_SHIFT is preconfigured in the example designs to meet the setup and hold constraints for the example GMII pinout in the particular device. The setup/hold timing which is achieved after place-and-route is reported in the data sheet section of the TRCE report (created by the implement script).

For customers fixing their own pinout, the setup and hold figures reported in the TRCE report can be used to initially setup the approximate DCM phase-shift. Appendix C, “Calculating DCM Phase-Shifting”describes a more accurate method for fixing the phase- shift by using hardware measurement of a unique PCB design.

Virtex-5 Devices

The GMII design uses IODELAY components on the receiver clock, data and control signals for Virtex-5 devices. A fixed tap delay can be applied to either delay the data and control signals or delay the clock so that the data/control are correctly sampled by the gmii_rx_clk clock at the IOB flip-flop, meeting GMII setup and hold timing.

The choice of delaying data/control or clock is dependant upon a number of factors, not least being the required shift. There are trade-offs to be made with either choice. Delaying the clock is clock-period specific as we move the clock to line up each edge with data from the following edge. Delaying the data/control introduces more jitter which degrades the overall setup/hold window. The interface timing report in the two cases is also quite different. See “Understanding Timing Reports for GMII Setup/Hold Timing.”

The following constraint shows an example of setting the delay value for one of these IODELAY components. Data/Control bits can be adjusted individually, if desired, to compensate for any PCB routing skew.

INST *gmii_interface/delay_gmii_rx_dv IDELAY_VALUE = 33;

The value of IDELAY_VALUE is preconfigured in the example designs to meet the setup and hold constraints for the example GMII pinout in the particular device. The setup/hold timing which is achieved after place-and-route is reported in the datasheet section of the TRCE report (created by the implement script).

When IDELAY or IODELAY primitives are instantiated with a fixed delay attribute, an IDELAYCTRL component must be also instantiated to continuously calibrate the individual input delay elements. The IDELAYCTRL module requires a reference clock, which is assumed to be an input to the example design delivered by CORE Generator. The most efficient way to use the IDELAYCTRL module is to lock the placement of the instance to the clock region of the device where the IDELAY/IODELAY components are placed. An example LOC constraint for the IDELAYCTRL module is shown commented out in the UCF. See the Virtex-5 User Guide and code comments for more information.

The following constraints are provided in the example design to link the instance of the IDELAYCTRL to the IODELAY components used on the GMII. These constraints aid the Xilinx tools in automatic IDELAYCTRL placement:

# Group IODELAY and IDELAYCTRL components to aid placement

INST "*gemac_block/gmii_interface/delay_gmii_rx_clk" HIODELAY_GROUP ="HIODELAY_GMII_GRP1"; INST "*gemac_block/gmii_interface/delay_gmii_rx_dv" HIODELAY_GROUP = "HIODELAY_GMII_GRP1"; INST "*gemac_block/gmii_interface/delay_gmii_rx_er" HIODELAY_GROUP = "HIODELAY_GMII_GRP1"; INST "*gemac_block/gmii_interface/*delay_gmii_rxd" HIODELAY_GROUP = "HIODELAY_GMII_GRP1"; INST "*gemac_block/dlyctrl" HIODELAY_GROUP = "HIODELAY_GMII_GRP1";

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		UG144 April 24, 2009