Xilinx UG144 manual Writing and Reading to and from the Configuration Registers

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Using the Optional Management Interface

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The Address Filter can be programmed to respond to four separate additional addresses stored in an address table in the Address Filter. Table 8-10and Table 8-11describe how the contents of the address table are set.

Table 8-10:Address Table Configuration Word 0

Bits	Default	Description
	Value
31–0	All 0s	MAC Address[31:0].
		The address is ordered so the first byte received is the
		lowest positioned byte in the register; for example, a MAC
		address of AA-BB-CC-DD-EE-FF would be stored in
		Address[47:0] as 0xFFEEDDCCBBAA.
Table 8-11:Address Table Configuration Word 1
Bits	Default	Description
	Value
15–0	All 0s	MAC Address[47:32].
17–16	All 0s	The location in the address table that the MAC address is
		to be written to or read from. There are up to 4 entries in
		the table (Location 0 to 3).
22–18	N/A	Reserved
23	0	Read not write This bit is set to ‘1’ to read from the address
		table. If it is set to ‘1,’ the contents of the table entry that is
		being accessed by the bits 17-16 will be output on the
		hostrddata bus in consecutive cycles (least significant
		word first). If it is set to ‘0,’ the data on bits 15-0 is written
		into the table at the address specified by bits 17-16.
31–24	N/A	Reserved

The contents of the Address Filter mode register are described in Table 8-12.

Table 8-12:Address Filter Mode

Bits	Default	Description
	Value
30–0	N/A	Reserved
31	0	Promiscuous Mode If this bit is set to ‘1,’ the Address Filter
		operates in promiscuous mode. All frames are passed to
		the receiver client, regardless of the destination address.

Writing and Reading to and from the Configuration Registers

Writing to the configuration registers through the management interface is shown in Figure 8-1. When accessing the configuration registers (when host_addr[9] = ‘1’ and host_miim_sel = ‘0’), the upper bit of host_opcode functions as an active low write enable signal. The lower host_opcode bit is a don’t care bit.

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UG144 April 24, 2009