Xilinx UG144 manual Reset Conditions, 4Clock Management Logic with External Rgmii Multiple Cores

R

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Chapter 10: Clocking and Resetting

DCM	BUFG
CLK_0
IBUFG
gtx_clk	BUFG
CLK_90

RGMII Tx Logic

1-Gigabit Ethernet MAC Core			BUFG	DCM
	gtx_clk	gmii_rx_clk		CLK_0

IBUFG

rgmii_rxc1

RGMII Rx Logic

1-Gigabit Ethernet MAC Core			BUFG	DCM
	gtx_clk	gmii_rx_clk		CLK_0

IBUFG

rgmii_rxc2

RGMII Tx Logic

RGMII Rx Logic

Figure 10-4:Clock Management Logic with External RGMII (Multiple Cores)

Reset Conditions

Internally, the core is divided up into clock/reset domains that group together elements with common clock and reset signals. The reset circuitry for one of these domains is illustrated in Figure 10-5. This circuit provides controllable skews on the reset nets within the design.

reset Configuration reset

PRE

'0' D Q

C

FDP

Clock

PRE D Q

C

FDP

PRE D Q

C

FDP

PRE D Q

C

FDP

Core Registers

PRE PRE PRE

Figure 10-5:Reset Circuit for a Single Clock/reset Domain

112	www.xilinx.com	1-Gigabit Ethernet MAC v8.5 User Guide
		UG144 April 24, 2009