Xilinx UG144 manual Access without the Management Interface, Pause frame MAC Source Address470

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Chapter 8: Configuration and Status

Access without the Management Interface

If the optional management interface is omitted from the core, all of the relevant configuration settings described in Table 8-3through Table 8-6are brought out of the core as signals. These signals are bundled into the configuration_vector[67:0] signal as described in Table 8-13.

These signals may permanently set by connecting to logic 0 or 1, or may be changed by the user application at any time; however, with the exception of the reset and the flow control configuration signals, any changes do not take effect until the current frame has completed transmission or reception.

The Clock heading in Table 8-13denotes which clock domain the configuration signal is registered into before use by the core. It is not necessary to drive the signal from this clock domain.

Table 8-13:Configuration Vector Bit Definition

	Configuration
Bit(s)	Register cross	Clock	Description
	reference
47:0	“Receiver	gmii_rx_clk	Pause frame MAC Source Address[47:0]
	Configuration		This address is used by the GEMAC core to
	Word 0” bits 31-0		match against the destination address of any
	and “Receiver		incoming flow control frames, and as the
	Configuration		source address for any outbound flow control
	Word 1” bits 15-0		frames.
			The address is ordered such that the first byte
			transmitted or received is the least significant
			byte in the register; for example, a MAC
			address of AA-BB-CC-DD-EE-FF will be
			stored in bite [47:0] as 0xFFEEDDCCBBAA.
48	n/a	n/a	This input is unused.
49	“Receiver	gmii_rx_clk	Receiver VLAN Enable When this bit is set to
	Configuration		'1,’ VLAN tagged frames are accepted by the
	Word 1” bit 27		receiver.
50	“Receiver	gmii_rx_clk	Receiver Enable If set to '1,’ the receiver
	Configuration		block is operational. If set to '0,’ the block
	Word 1” bit 28		ignores activity on the physical interface RX
			port.
51	“Receiver	gmii_rx_clk	Receiver In-band FCS Enable When this bit
	Configuration		is ‘1,’ the MAC receiver will pass the FCS
	Word 1” bit 29		field up to the client. When it is ‘0,’ the MAC
			receiver will not pass the FCS field. In both
			cases, the FCS field will be verified on the
			frame.
52	“Receiver	gmii_rx_clk	Receiver Jumbo Frame Enable When this bit
	Configuration		is ‘0,’ the receiver will not pass frames longer
	Word 1” bit 30		than the maximum legal frame size specified
			in IEEE 802.3-2005. At ‘1,’ the receiver will not
			have an upper limit on frame size.

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		UG144 April 24, 2009