Xilinx UG144 manual Using the Mdio interface, Connecting the Mdio to an Internally Integrated PHY

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Chapter 7: Using the Physical Side Interface

Using the MDIO interface

The MDIO interface is accessed through the optional management interface and is typically connected to the MDIO port of a physical-layer device to access its configuration and status registers (see “MDIO Interface,” on page 86). The MDIO format is defined in IEEE 802.3, clause 22.

Connecting the MDIO to an Internally Integrated PHY

The MDIO ports of the GEMAC core can be connected to the MDIO ports of an internally integrated physical-layer device, such as the MDIO port of the Xilinx Ethernet 1000BASE- X PCS/PMA or SGMII core. See Chapter 11, “Interfacing to Other Cores” for more information.

Connecting the MDIO to an External PHY

The MDIO ports of the GEMAC core can be connected to the MDIO of an external physical-layer device. In this situation, mdio_in, mdio_out, and mdio_tri must be connected to a tri-state buffer to create a bidirectional wire, mdio. This tri-state buffer can be either external to the FPGA, or internally integrated by using an IOB IOBUF component with an appropriate SelectIOTM standard for the external PHY (illustrated in Figure 7-11).

1-Gigabit Ethernet MAC Core

IOB LOGIC

mdc

OBUF

I O

OPAD MDC

mdio_tri

mdio_out

mdio_in

IOB LOGIC

IOBUF

T
I	IOPAD MDIO
	IO
O

Figure 7-11:Creating an External MDIO Interface

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		UG144 April 24, 2009