Xilinx UG144 manual Interfaces, Transmit Fifo, Appendix a Using the Client-Side Fifo

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Appendix A: Using the Client-Side FIFO

Interfaces

Transmit FIFO

Table A-1describes the transmit FIFO client interface. For more information on the MAC client interface, see “Transmitting Outbound Frames,” on page 47.

Table A-1:Transmit FIFO Client Interface

Signal

Direction

Clock

Description

Domain

 

 

 

 

 

 

 

tx_clk

Input

N/A

Transmit clock used by MAC.

 

 

 

 

tx_reset

Input

tx_clk

Synchronous reset.

 

 

 

 

tx_enable

Input

tx_clk

Clock enable for tx_clk. Tie to logic 1

 

 

 

when using GEMAC.

 

 

 

 

tx_data[7:0]

Output

tx_clk

Data presented t o MAC for

 

 

 

transmission.

 

 

 

 

tx_data_valid

Output

tx_clk

Valid signal for data.

 

 

 

 

tx_ack

Input

tx_clk

Ack signal from MAC.

 

 

 

 

tx_underrun

Output

tx_clk

Underrun signal to MAC.

 

 

 

 

tx_collision

Input

tx_clk

Collision indication from MAC. Tie

 

 

 

to logic 0 when using GEMAC.

 

 

 

 

tx_retransmit

Input

tx_clk

Retransmit request from MAC. Tie to

 

 

 

logic 0 when using GEMAC.

 

 

 

 

Table A-2describes the transmit FIFO LocalLink interface. For more information on the LocalLink interface see “Overview of LocalLink Interface,” on page 130.

Table A-2:Transmit FIFO LocalLink Interface

Signal

Direction

Clock

Description

Domain

 

 

 

 

 

 

 

tx_ll_clock

Input

N/A

Write clock for LocalLink interface

 

 

 

 

tx_ll_reset

Input

tx_ll_clock

Synchronous reset

 

 

 

 

tx_ll_data_in[7:0]

Input

tx_ll_clock

Write data to be sent to transmitter

 

 

 

 

tx_ll_sof_in_n

Input

tx_ll_clock

Start of frame indicator

 

 

 

 

tx_ll_eof_in_n

Input

tx_ll_clock

End of frame indicator

 

 

 

 

tx_ll_src_rdy_in_n

Input

tx_ll_clock

Source ready indicator

 

 

 

 

tx_ll_dst_rdy_out_n

Output

tx_ll_clock

Destination ready indicator

 

 

 

 

tx_fifo_status[3:0]

Output

tx_ll_clock

FIFO memory status

 

 

 

 

tx_overflow

Output

tx_ll_clock

Overflow signal indicates when a

 

 

 

frame has been dropped in the FIFO

 

 

 

 

128

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1-Gigabit Ethernet MAC v8.5 User Guide

 

 

UG144 April 24, 2009

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Xilinx UG144 manual Interfaces, Transmit Fifo, Appendix a Using the Client-Side Fifo