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Xilinx UG144 manual Virtex-5 FXT Devices, Clkdv

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Chapter 11: Interfacing to Other Cores

•Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE-X PCS/PMA or SGMII core, the entire GMII is synchronous to a single clock domain. For this reason, userclk2 is used as the 125 MHz reference clock for both cores and the transmitter and receiver logic of the GEMAC core now operate in the same clock domain. This allows clock crossing constraints between the gtx_clk and gmii_rx_clk clock domains to be removed from the GEMAC UCF. See “Timespecs for Critical Logic within the Core.”

Virtex-5 FXT Devices

Figure 11-4illustrates the connections and clock management logic required to interface the GEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in 1000BASE-X mode with PMA using the device-specific RocketIO transceiver).

DCM	BUFG	userclk2 (125MHz)
CLKIN CLK0		userclk2 (125MHz)
CLKIN CLK0
FB	BUFG	userclk (62.5MHz)
CLKDV		userclk (62.5MHz)
CLKDV

component_name_block

(Block Level from example design)


brefclkp			IBUFGDS
IPAD

IPAD			clkin

brefclkn			(125MHz)

1-Gigabit Ethernet

MAC

LogiCORE

gtx_clk

gmii_rx_clk

gmii_txd[7:0] gmii_tx_en

gmii_tx_er

gmii_rxd[7:0]

gmii_rx_dv gmii_rx_er

mdc

mdio_in

mdio_out

mdio_tri no connection

Ethernet 1000BASE-X

PCS/PMA or SGMII

LogiCORE

gmii_txd[7:0]

gmii_tx_en

userclk

gmii_tx_er userclk2

gmii_rxd[7:0]

gmii_rx_dv gmii_rx_er

mdc

mdio_in

mdio_out

mdio_tri

RocketIO I/F

Virtex-5

GTX

RocketIO

REFCLKOUT

CLKIN

TXUSRCLK0

TXUSRCLK20

RXUSRCLK0

RXUSRCLK20

Figure 11-4:1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

using the RocketIO transceiver

118	www.xilinx.com	1-Gigabit Ethernet MAC v8.5 User Guide
		UG144 April 24, 2009

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Xilinx UG144 manual Virtex-5 FXT Devices, Clkdv

Contents

LogiCORE IP Gigabit Ethernet MAC UG144 April 24Gigabit Ethernet MAC v8.5 User Guide Revision History Date Version RevisionDIS Product Table of Contents Designing with the Core Configuration and Status Appendix C Calculating DCM Phase-Shifting 1Block Diagram Schedule of Figures2External Gmii Receiver Logic for Spartan-3, Spartan-3E, Figure A-2Frame Transfer across LocalLink Interface DIS Product Schedule of Tables Clocking and Resetting Interfacing to Other Cores Guide Contents About This GuidePreface About This Guide ConventionsTypographical Convention Meaning or Use ExampleConventions Online DocumentList of Acronyms Acronym Spelled OutPreface About This Guide Acronym Spelled Out VhdlAbout the Core Related Xilinx Ethernet Products and ServicesIntroduction Recommended Design ExperienceFeedback SpecificationsTechnical Support Gemac CoreCore Architecture System OverviewCore Components Gmac Core with Optional Management Interface Core InterfacesCore Interfaces Core Architecture Core Interfaces Client Side Interface Transmitter InterfaceReceiver Interface Flow Control InterfaceManagement Interface Optional MAC Unicast Address Optional7Reset Signal Direction Clock Domain Description Configuration Vector OptionalAsynchronous Reset Physical Side InterfaceMdio Interface Generating the Core Graphical User InterfaceParameter Values in the XCO File Output Generation Generating the Core General Design Guidelines Using the Example Design as a Starting PointDesigning with the Core Design StepsDesigning with the Core 11-Gigabit Ethernet MAC Core Example DesignImplementing the 1-Gigabit Ethernet MAC in Your Application Know the Degree of DifficultyGeneral Design Guidelines Use Supported Design Flows Recognize Timing Critical SignalsKeep it Registered Make Only Allowed ModificationsReceiving Inbound Frames Using the Client Side Data Path1Abbreviations Used in Timing Diagrams Definition Normal Frame ReceptionUsing the Client Side Data Path Rxgoodframe, rxbadframe timingFrame Reception with Errors Receiving Inbound FramesClient-Supplied FCS Passing Vlan Tagged FramesDisabled Length/Type Field Error ChecksEnabled Maximum Permitted Frame LengthReceiver Statistics Vector 5Receiver Statistics Vector TimingDIS Product Length see Maximum Permitted Frame Padding Transmitting Outbound FramesNormal Frame Transmission Transmitting Outbound FramesClient Underrun 7Frame Transmission with Client-supplied FCSInter-Frame Gap Adjustment 9Transmission of a Vlan Tagged Frame10Inter-Frame Gap Adjustment Transmitter Statistics VectorName Bit 31 is equivalent to bit Overview of Flow Control Using Flow ControlFlow Control Requirement Using Flow Control Flow Control BasicsPause Control Frames Overview of Flow ControlCore-initiated Pause Request Flow Control Operation of the GemacTransmitting a Pause Control Frame Client Initiated Pause RequestClient Initiated Response to a Pause Request Receiving a Pause Control FrameCore Initiated Response to a Pause Request Flow Control Operation of the GemacFlow Control Implementation Example MethodFlow Control Implementation Example 4Flow Control Implementation Triggered from Fifo OccupancyUsing Flow Control Implementing External Gmii Using the Physical Side InterfaceGmii Transmitter Logic Using the Physical Side Interface 1External Gmii Transmitter LogicSpartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices Gmii Receiver LogicImplementing External Gmii DCM Reset circuitry Virtex-5 Devices 3External Gmii Receiver Logic for Virtex-5 DevicesImplementing External Rgmii Rgmii Transmitter LogicVirtex-4 Devices Implementing External Rgmii5External Rgmii Transmitter Logic in Virtex-4 Devices 6External Rgmii Transmitter Logic in Virtex-5 Devices Rgmii Receiver Logic 7External Rgmii Receiver Logic Virtex-4 Devices 8External Rgmii Receiver Logic for Virtex-4 Devices 9External Rgmii Receiver Logic for Virtex-5 Devices Rgmii Inband Status Decoding Logic 10RGMII Inband Status Decoding LogicConnecting the Mdio to an Internally Integrated PHY Using the Mdio interfaceConnecting the Mdio to an External PHY Using the Optional Management Interface Configuration and StatusHost Clock Frequency Configuration and Status Configuration Registers2Configuration Registers Address Description 3Receiver Configuration Word Bit Default Description Receiver ConfigurationUsing the Optional Management Interface Receiver Configuration WordTransmitter Configuration Interframe Gap Adjust Enable If ‘1,’ the transmitter willFlow Control Configuration 6Flow Control Configuration Word Bit Default DescriptionMdio Configuration Address Filter Configuration11 Address Table Configuration Word Writing and Reading to and from the Configuration Registers10Address Table Configuration Word Bits Default Description 12Address Filter Mode Bits Default Description1Configuration Register Write Timing Accessing the Address Table 3Address Table Write TimingMdio Interface Introduction to MdioWrite Transaction 5Typical MDIO-managed SystemAccessing Mdio With Gemac Read Transaction8MDIO Access through Management Interface Access without the Management Interface Pause frame MAC Source Address470Transmitter Interframe Gap Adjust Enable Receive Flow Control Enable . When this bit Constraining the Core Required ConstraintsPeriod Constraints for Clock Nets Constraining the CoreTimespecs for Critical Logic within the Core Required ConstraintsTimespecs for Reset Logic within the Core Constraints when Implementing an External GmiiGmii IOB Constraints Gmii Input Setup/Hold Timing 1Input Gmii Timing Symbol Min Max UnitsVirtex-5 Devices Virtex-5 devices with Delayed Data/Control Understanding Timing Reports for Gmii Setup/Hold TimingNon-Virtex-5 devices Virtex-5 Devices with Delayed Clock Constraints when Implementing an External Rgmii Rgmii IOB ConstraintsRgmii Input Setup/Hold Timing 2Input Rgmii Timing Symbol Min Typical UnitsSpartan-3, Spartan-3E, Spartan-3A, and Virtex-4 Devices Rgmii DDR Constraints Understanding Timing Reports for Rgmii Setup/Hold timing 106 4Timing Report Setup/Hold Illustration 108 With Internal Gmii Clocking and ResettingClocking the Core With External GmiiWith Rgmii Clocking and ResettingMultiple Cores Standard Clocking SchemeMultiple Cores 3Clock Management Logic with External Gmii Multiple CoresReset Conditions 4Clock Management Logic with External Rgmii Multiple CoresInterfacing to Other Cores Ethernet 1000Base-X PCS/PMA or Sgmii CoreIntegration to Provide 1000BASE-X PCS with TBI Interfacing to Other CoresEthernet 1000Base-X PCS/PMA or Sgmii Core 116 Virtex-5 LXT and SXT Devices GTPVirtex-5 FXT Devices ClkdvIntegration to Provide Sgmii Functionality Ethernet Statistics CoreEthernet Statistics Core 120 Configuration Miim access Statistics Read 122 Pre-implementation Simulation Using the Simulation ModelImplementing Your Design SynthesisGenerating the Xilinx Netlist ImplementationXST-Verilog Mapping the DesignStatic Timing Analysis Post-Implementation SimulationPlacing-and-Routing the Design Generating a BitstreamUsing the Model Other Implementation InformationUsing the Client-Side Fifo GMII/RGMIIInterfaces Appendix a Using the Client-Side FifoTransmit Fifo Receive Fifo InterfacesOverview of LocalLink Interface Data FlowClock Requirements Functional OperationFunctional Operation Expanding Maximum Frame Size User Interface Data Width ConversionVerification by Simulation Core Verification, Compliance, and InteroperabilityHardware Verification 134 DCM Phase-Shifting Calculating DCM Phase-ShiftingFinding the Ideal Phase-Shift Appendix C Calculating DCM Phase-Shifting Transmit Path Latency Core LatencyReceive Path Latency Appendix D Core Latency