Multiple Cores, With Rgmii, Standard Clocking Scheme

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Chapter 10: Clocking and Resetting

With RGMII

Standard Clocking Scheme

Figure 10-2illustrates the clock management used with an external RGMII interface. All clocks illustrated have a frequency of 125 MHz. The gtx_clk clock must be provided to the GEMAC core. This is a high-quality clock that satisfies IEEE 802.3-2005requirements. It is expected that this clock will be derived from an external oscillator and connected into the device through an IBUFG as illustrated in Figure 10-2. This clock is used as the input clock to a DCM from where phase-shifted clock signals are generated for use in the RGMII transmitter logic. The zero phase-shifted clock is used as the input gtx_clk to the GEMAC core.

The receiver clock, rgmii_rxc is usually derived from a different clock source to

gtx_clk. In this case, rgmii_rxc will be received through an IBUFG. This clock is routed into a DCM where it is used to generate phase-shifted clock signals for use in the RGMII receiver logic. A fixed phase-shift value is applied to the DCM to meet RGMII setup and hold requirements. See Appendix C, “Calculating DCM Phase-Shifting.”The zero clock is used as the input gmii_rx_clk to the GEMAC core.

DCM BUFG

CLK_0

IBUFG

gtx_clk

BUFG

1-Gigabit Ethernet

MAC Core

gtx_clk gmii_rx_clk

BUFG DCM

CLK_0

IBUFG

rgmii_rxc

CLK_90

RGMII Tx Logic

RGMII Rx Logic

Figure 10-2:Clock Management with External RGMII

Multiple Cores

With External GMII

Figure 10-3illustrates how to share clock resources across multiple instantiations of the core when using the optional GMII. gtx_clk may be shared between multiple cores as illustrated, resulting in a common transmitter clock domain across the device.

A common receiver clock domain is usually not possible as each core will receive an independent receiver clock from the PHY attached to the other end of the GMII. As illustrated in Figure 10-3, this results in a separate receiver clock domain for each core.

110	www.xilinx.com	1-Gigabit Ethernet MAC v8.5 User Guide
		UG144 April 24, 2009

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.

Xilinx UG144 manual Multiple Cores, With Rgmii, Standard Clocking Scheme, Clocking and Resetting

Models: UG144